TeraPool-SDR: 1024-Core SDR Cluster

• TeraPool-SDR is a scalable 1024-core RISC-V many-core cluster designed for next-generation SDR workloads in 5G/6G RANs, featuring a shared 4 MiB L1 scratchpad organized in 4096 banks.
• The architecture employs advanced data folding, fine-grained tiling, and hierarchical interconnects to achieve up to 1.89 TOPS and 125 GOPS/W, ensuring high throughput and energy efficiency.
• Its programmable fork-join C runtime and parallel programming model enable efficient mapping of baseband processing kernels, delivering real-time performance within stringent base station power budgets.

TeraPool-SDR is a scalable, 1024-core RISC-V many-core cluster specifically designed for extreme computational efficiency in next-generation software-defined radio (SDR) workloads, with a focus on 5G and 6G radio access networks (RANs). It integrates a single shared 4 MiB L1 scratchpad memory, organized into 4096 banks, and leverages a hierarchical on-chip interconnect to deliver both high throughput and energy efficiency within base station power budgets. TeraPool-SDR demonstrates that a fully programmable many-core approach, as opposed to fixed-function accelerators, can meet the stringent demands of real-time massive-MIMO SDR baseband processing, achieving up to 1.89 TOPS and 125 GOPS/W in 12 nm FinFET technology (Zhang et al., 2024).

1. Architectural Organization and Processing Elements

TeraPool-SDR comprises 1024 RISC-V "Snitch" cores (processing elements, or PEs) grouped into 128 Tiles, with each Tile containing 8 cores. The memory subsystem is a globally addressable 4 MiB L1 scratchpad (SPM) split across 4096 single-ported SRAM banks, offering uniform access latency via a layered network.

The organization is as follows:

Level	Units per Level	Internal Interconnect
Tile	8 PEs, 32 L1 banks	40×32 FC crossbar
SubGroup	8 Tiles	4 × 8×8 FC crossbars
Group	4 SubGroups	32×32 FC crossbar
Cluster	4 Groups (2×2)	Inter-Group links (+2–6 cycles)

Each Snitch PE is a 32-bit, single-stage, in-order RISC-V core (RV32), with an offload accelerator port for pipelined FPU/DSP operation and multiple-outstanding load/store transactions. It maintains a 32-entry instruction queue (I\$L0) and 4 KiB 2-way L1 I\$ per core for code refills (Zhang et al., 2024).

The architecture enables latency tolerance: memory requests can be issued speculatively, hiding zero-load memory latency up to 11 cycles for remote-group banks as long as the core’s outstanding request capability $P\geq L_m$ (parallel load slots ≥ worst-case latency in cycles).

2. Memory Subsystem and Interconnect Topology

TeraPool-SDR’s shared L1 SPM consists of 4096 banks × 1 KiB each. The bank-interleaved address mapping $(\text{bank index} = (\text{addr}/4) \bmod 4096)$ distributes consecutive 32-bit words across different banks, maximizing parallelism and minimizing conflicts.

Interconnect details:

• Tile-local: 40×32 fully-connected crossbar links 8 PEs and 32 banks for 1 cycle latency.
• SubGroup: Four 8×8 FC crossbars connect 8 Tiles to 8 SubGroup banks, 3-cycle zero-load access.
• Group: Each of 4 Groups includes a 32×32 FC crossbar (5-cycle local, 7–11 cycles inter-group with damping registers).
• Bandwidth ceilings: Each PE can issue 1 request/cycle; at $f=800$ MHz and per-core saturation $\lambda_{\text{sat}}\approx0.24$ req/core/cycle, aggregate bandwidth is approximately 0.79 TB/s (Zhang et al., 2024).

A global uniform address space permits efficient fork-join programming, with data-coherence and bank-placement policies coordinated by software.

3. Software and Parallel Programming Model

TeraPool-SDR employs a fork-join C runtime, exposing APIs such as parallel_get_core_id() and low-latency parallel_barrier() for global and hierarchical (per-tile, subgroup) synchronization. The programming model allows each core to operate autonomously on its local memory partition, with DMA engine support for moving data between global L2 and Tile-local L1 via double-buffering.

Parallelization strategies are designed to match the memory hierarchy:

• Dense matrix compute kernels (e.g., matrix-matrix multiplication) are tiled and "folded" so each PE’s working set maps to distinct banks, minimizing crossbar contention.
• Vector/FFT kernels are partitioned across streams, with per-stage barrier synchronization to handle dependency and data movement.
• Task replication is leveraged for subproblem multiplicity (e.g., processing multiple FFTs or Cholesky decompositions in parallel).

Example kernel (4096-point FFT, 64 streams; see (Zhang et al., 2024)):

$P\geq L_m$3

4. SDR and 5G/6G PHY Workload Mapping

TeraPool-SDR targets lower PHY signal-processing kernels in 5G RANs, especially those for uplink shared channel (PUSCH) reception. The key algorithmic stages are:

1. OFDM demodulation (fast Fourier transform),
2. Beamforming (matrix-matrix multiplication, MMM),
3. Channel estimation (element-wise vector/matrix division),
4. MIMO equalization (Cholesky decomposition, triangular solves),
5. Noise estimation (autocorrelation).

These stages are mapped as follows:

Kernel	Problem size	Cycles (1024 PEs, 730 MHz)	IPC	GOPS/W (at 925 MHz)
FFT	$64\times4096$	32,012	0.75	93
MatMul	$512\times512$	298,239	0.69	125
CHE	$(32\times4)\times4096$	17,221	0.64	96
SysInv	$(4\times4)\times65,536$	31,254	0.59	61

The entire PUSCH receive chain (for one 5G payload: 14 OFDM symbols, $N_{SC}=3276$, $P\geq L_m$0, $P\geq L_m$1, $P\geq L_m$2) processes in 785,000 cycles at 1 GHz, i.e., 0.785 ms per payload, with aggregate speedup of 871× over a single core baseline (Bertuletti et al., 2022, Zhang et al., 2024).

5. Physical Implementation and Power-Performance-Area Results

TeraPool-SDR was fully physically implemented in GF 12 nm LPplus FinFET, occupying 68.9 mm² in its principal configuration. Area per core is 0.067 mm², with each Tile (8 cores + 32 banks) consuming 1.52×1.52 mm at 55% utilization. Zero-load local bank access latency is 6.4 cycles (average), and remote-group latency varies from 7 to 11 cycles depending on pipeline placement in the interconnect (Zhang et al., 2024).

Operating frequency is 730 MHz (typical, TT/0.80 V/25 °C), scaling to 924 MHz in energy-optimized corners. The design sustains up to 1.89 TOPS, with area efficiency of 21.8 GOPS/mm².

Power consumption per kernel:

Kernel	Power [W]
FFT	6.5
MatMul	8.8
Channel Estimation	6.6
System Inversion	4.9

All kernels execute under 10 W, compatible with industry RAN base-station budgets.

6. Scalability, Bottlenecks, and Future Directions

TeraPool-SDR achieves >80% core utilization on critical 5G/6G kernels. The memory banking strategy—data folding, fine-grained tiling, and careful bank assignment—keeps load-store unit stalls (bank conflicts, remote latency) below 10% of cycles. Synchronization latency is amortized by batching parallel jobs between barriers; the fork-join runtime supports efficient single and partial barriers using hierarchical counter/CSR and WFI mechanisms (Bertuletti et al., 2022).

Scalability is limited by BEOL congestion and EDA runtime of large crossbars (e.g., 32×32 per Group). Beyond 1000 cores, the feasibility of monolithic, planar shared-L1 clusters is challenged, suggesting the need for 3D-IC integration or network-in-package approaches to constrain wirelengths and allow further scaling.

Proposed future extensions include lightweight floating-point accelerators, automated placement/routing for even larger clusters, and full-system 5G/6G RAN integration including L2/L3 memory and external RF front-ends (Zhang et al., 2024). Further ISA extensions (e.g., FFT butterfly, fused MAC) are estimated to improve kernel performance by 30%.

TeraPool-SDR thus provides a reference platform for open-source, high-efficiency, and fully programmable SDR cluster design suitable for next-generation multi-antenna wireless systems.