Takum Arithmetic: Enhanced Tapered-Precision

• Takum arithmetic is a tapered-precision number format that dynamically allocates exponent and fraction bits to achieve a symmetric, bounded dynamic range, enhancing numerical robustness in high-performance computing.
• It employs adaptive precision to ensure a lower bound on fraction bits, thereby outperforming IEEE 754 and posit formats in both low and high precision scenarios.
• Efficient hardware encoding and strong closure properties make Takum arithmetic ideal for advanced computations in linear algebra, signal processing, and scientific computing.

Takum arithmetic is a modern machine number format belonging to the family of tapered-precision representations. Developed as an enhancement over posit arithmetic, takum combines efficient logarithmic exponent encoding and adaptive precision allocation to achieve bounded, symmetric dynamic range and robust numerical properties. It directly targets applications in high-performance computing, numerical linear algebra, signal processing, and hardware acceleration where IEEE 754 and posit formats often exhibit practical limitations.

1. Format Definition and Internal Encoding

Takum numbers are parameterized by total bit-width $n$ and are structured to enable dynamic allocation of bits between exponent and fraction, tailored by the number’s magnitude. For all %%%%1%%%%, the canonical encoding for linear takum is as follows (Hunhold, 2024, Hunhold, 2024, Hunhold, 2024):

• Fields (MSB → LSB)
  • 1 sign bit $S$
  • 1 direction bit %%%%3%%%%
  • 3 regime bits $R = (R_2, R_1, R_0)$, for regime count $r\in\{0,\ldots,7\}$
  • $r$ characteristic (exponent) bits $C$
  • $p = n - 5 - r$ fraction (mantissa) bits $M$
• Regime decoding depends on $D$:

$$r = \begin{cases} 7-(4R_2+2R_1+R_0) & \text{if}\ D=0\ \ \ \;4R_2+2R_1+R_0 & \text{if}\ D=1 \end{cases}$$

$C$ encodes

$$c = \begin{cases} -2^{r+1} + 1 + \text{uint}(C) & D=0 \ 2^r - 1 + \text{uint}(C) & D=1 \end{cases}$$

$M$ encodes a fraction $f = \text{uint}(M)/2^p$.

• Value mapping:

$$\tau(T) = \begin{cases} 0 & S=0,\ D=R=C=M=0 \ \mathrm{NaR} & S=1,\ D=R=C=M=0 \ (1+f) \cdot 2^e & \text{otherwise} \end{cases}$$

with $e = c$.

This encoding supports both the linear takum (floating-point-like) and the logarithmic takum (LNS-like) instantiations (Hunhold, 2024).

2. Dynamic Range and Precision Properties

Takum arithmetic provides a dynamic range that becomes constant and symmetric once $n \geq 12$, with exponents spanning $|e| \le 255$ (Hunhold, 2024, Hunhold, 2024). The value domain encompasses

$|x| \in [2^{-255}, 2^{254}]$

in the linear form, and $[e^{-255}, e^{255}]$ in the logarithmic variant. This property sharply distinguishes takum from posit and IEEE 754 floats, where the dynamic range grows logarithmically and remains limited at small $n$.

Precision is tapered and explicitly lower-bounded: for any magnitude, the number of fraction bits satisfies $p \geq n-12$. This ensures, for $n\geq64$, that takum maintains at least float64-comparable machine epsilon, but, unlike posits, never exhausts all fraction bits—critical for both worst-case and average-case rounding error bounds (Hunhold, 2024, Hunhold, 2024).

Near unity, takum exhibits slightly lower local precision than posit of the same width, but at extreme magnitudes (large $|e|$) it surpasses both IEEE 754 and posit in bit efficiency and relative spacing (Hunhold, 2024, Hunhold et al., 29 Apr 2025).

3. Arithmetic Algorithms and Rounding Behavior

Takum multiplication, division, inversion, and root computations reduce to integer arithmetic (in LNS form) or fixed-point exponent/significand operations (in linear form), with all encoding/decoding confined to the uppermost twelve bits for $n\geq12$ (Hunhold, 2024, Hunhold, 2024). Addition and subtraction are more complex in LNS form, requiring a table-lookup/logarithmic correction (Gaussian logarithms), but are standard for linear takum.

Rounding to nearest, round-to-even, and saturation semantics are directly supported. Overflow or underflow lead to saturation at the extremal representable value, not multiple codes or silent wrapping (Hunhold, 2024, Hunhold, 2024). The bounded fraction bits guarantee that worst-case machine epsilon is never larger than $2^{-(n-12)}$ at any magnitude.

Operational closure is significantly enhanced: inversion, multiplication, division, square, and square-root for takums achieve 100% exact results in empirical evaluation, while IEEE and posit counterparts may introduce unavoidable rounding (Hunhold, 2024).

4. Integer Representation and Bit-Width Efficiency

A distinguishing strength of takum arithmetic is its capacity for exact encoding of large integers within a given bit width. This is characterized by an explicit closed-form bound (Hunhold, 2024):

$$N_{\max}(n) = 2^{\left\lceil \frac{W_0(2^{n-3}\ln2)}{\ln2} - 1 \right\rceil }$$

where $W_0$ is the principal branch of the Lambert $W$ function.

Comparison against IEEE 754 and posit formats reveals that takum matches or surpasses them in largest consecutive integer capacity for $n \geq 32$, which is crucial for algorithms sensitive to index range (e.g. quantized neural networks, blockchains) (Hunhold, 2024).

$n$ (bits)	Takum $N_{\max}(n)$	IEEE 754 (single/double)	Posit
16	$2^9 = 512$	$2^{11}=2048$	$<$Takum
32	$2^{24}\approx1.68 \times 10^7$	$2^{24}$	$<$Takum
64	$2^{55}\approx3.6 \times 10^{16}$	$2^{53}$	$<$Takum

As the table shows, takum’s largest consecutive integer strictly exceeds IEEE 754 and posit for 32 and 64 bits (Hunhold, 2024).

5. Experimental Performance in Scientific Computing

Comprehensive benchmarks have evaluated takum arithmetic in PDE solvers, spectral transforms, sparse linear solvers, and eigensolvers (Hunhold et al., 29 Apr 2025, Hunhold et al., 2024, Hunhold et al., 29 Apr 2025):

• FFT/PDEs: Takum8/16 are the only low-precision formats, aside from posit8/16, not to overflow, outperforming bfloat16 and all OFP8 types by 1–2 orders of magnitude on relative error in heat and Poisson solvers. At 32/64 bits, takum matches float32/64 in accuracy but maintains higher dynamic-range margin and greater numerical robustness.
• Sparse Linear Solvers: Takum arithmetic yields accuracy and stability substantially superior to IEEE 754 and bfloat16 at 8–16 bits, with direct LU/QR and ILU-preconditioned GMRES solvers converging more rapidly and reliably. MPIR using takum accelerates convergence and tolerates extremely ill-conditioned matrices (Hunhold et al., 2024).
• Eigenvalue Problems: When using the implicitly restarted Arnoldi method, takums avoid the convergence failures and dynamic-range overflows observed in posit and IEEE 754 at all precisions. Relative error is consistently lower or on par with the highest-performing reference formats (Hunhold et al., 29 Apr 2025).

A key insight is that, at low precisions (8/16 bits), takum ensures practical viability of numerically demanding algorithms, while at higher precisions (32/64) it equals or surpasses IEEE 754 and posit in accuracy and stability (Hunhold et al., 29 Apr 2025, Hunhold et al., 2024, Hunhold et al., 29 Apr 2025).

6. Hardware Implementation and Architectural Considerations

Takum arithmetic is designed to lend itself to efficient hardware implementation. The dominant features are (Hunhold, 2024, Hunhold, 18 Mar 2025):

• Bounded decoding/encoding complexity: All exponent, regime, and characteristic field calculations are confined to the upper 12 bits, independent of $n$, using a small set of lookup tables and combinational logic. This yields a decoder latency that remains essentially constant as $n$ increases ($\approx$3.66 ns for $n=64$), while posit decoder latency grows by nearly 38%.
• Low LUT Footprint: On FPGA (Kintex UltraScale+), takum decoder logic consumes half as many CLB-LUTs as posit at $n=64$, with encoder logic also scaling favorably (Hunhold, 2024).

$n$	Takum decoder LUTs	Posit decoder LUTs	Takum decoder latency (ns)	Posit decoder latency (ns)
64	125	250	3.66	5.86

• Architectural Uniformity: Takum enables a single, shared decoder across all bit-widths within SIMD instructions, streamlining instruction set architectures (e.g. AVX10.2), reducing opcode proliferation, and simplifying pipeline control logic compared to IEEE 754 or posit (Hunhold, 18 Mar 2025).
• Hardware Multiplexing: The decoder and encoder parameterization by bit-width and exponent mode eliminates costly run-time multiplexers and wide shifters required in posit designs. All increment logic can be implemented via 8-bit CARRY8 primitives on common FPGAs (Hunhold, 2024).

7. Theoretical Guarantees and Proven Properties

Takum arithmetic exhibits several formally proven properties (Hunhold, 2024, Hunhold, 2024):

• No codepoint wastage: All $2^n$ bit patterns, except a single Not-a-Real (NaR), correspond to valid, distinct real numbers.
• Monotonic ordering: Bit patterns follow two’s-complement order, facilitating hardware comparison.
• Perfect invertibility: Bitwise negation and inversion are implemented by fixed rules, ensuring $1/x$ is exactly representable for any $x$ in the value range.
• Lower-bound on fraction bits: At least $n-13$ mantissa bits are guaranteed, supporting computation within $\frac{2}{3}$ the machine epsilon of IEEE 754.
• Closure under core arithmetic: Empirically, takums show 100% exact closure for inversion, multiplication, division, squaring, and square root, and competitive closure for addition/subtraction at a much higher dynamic range than posit or float of same width.

These properties, together with implementation efficiency and consistency across workloads, delineate takum as a robust, general-purpose tapered-precision number system for both hardware and software applications.

• "Spectral Methods via FFTs in Emerging Machine Number Formats: OFP8, Bfloat16, Posit, and Takum Arithmetics" (Hunhold et al., 29 Apr 2025)
• "Integer Representations in IEEE 754, Posit, and Takum Arithmetics" (Hunhold, 2024)
• "Evaluation of Bfloat16, Posit, and Takum Arithmetics in Sparse Linear Solvers" (Hunhold et al., 2024)
• "Beating Posits at Their Own Game: Takum Arithmetic" (Hunhold, 2024)
• "Streamlining SIMD ISA Extensions with Takum Arithmetic: A Case Study on Intel AVX10.2" (Hunhold, 18 Mar 2025)
• "Numerical Performance of the Implicitly Restarted Arnoldi Method in OFP8, Bfloat16, Posit, and Takum Arithmetics" (Hunhold et al., 29 Apr 2025)
• "Design and Implementation of a Takum Arithmetic Hardware Codec in VHDL" (Hunhold, 2024)