Switching-Synchronized Sampled State-Space (5S)

• Switching-Synchronized Sampled State-Space (5S) is an event-driven, discrete-time framework that models power converters by aligning sampling with each switching event instead of a fixed clock.
• It leverages single-cycle causality by choosing sampled variables that match converter switching logic, yielding cycle-by-cycle state updates and accurate control-oriented representations.
• The methodology facilitates direct digital design by deriving z-domain transfer functions and integrating both small-signal and large-signal models for advanced converter control.

Searching arXiv for the cited 5S and related switched sampled-state-space papers. arXiv search query: (Cui et al., 2022, Qian et al., 14 Jul 2025, Coënt et al., 2019, Tariverdi, 2 Nov 2025) "switching-synchronized sampled-state space" Switching-Synchronized Sampled State-Space, abbreviated 5S, denotes a sampled-state-space framework in which sampling and control updates are synchronized to switching events rather than to a uniform clock. In the formulation explicitly introduced for variable-frequency DC-DC converters, each switching cycle has a single sampling event and a corresponding single control action; these events are time-varying in physical time whenever the switching period varies, but remain synchronized to switching events (Cui et al., 2022). Subsequent work applies the same terminology to derive control-oriented cycle-by-cycle models for variable-frequency series-capacitor buck converters, where output-voltage sampling, controller update, reference-current update, and the start of the next on-time interval all occur at a comparator event (Qian et al., 14 Jul 2025). In this sense, 5S is a modeling and control viewpoint for event-driven, cycle-indexed switched systems whose natural discrete-time description is organized around switching instants.

1. Definition and conceptual scope

The defining feature of 5S is that the discrete-time index counts switching cycles or switching-triggered events, not uniformly spaced wall-clock samples. In the 2022 formulation, the sampled-state space is synchronized to switching events rather than to a uniform clock, and the resulting control is both event-driven and cycle-by-cycle (Cui et al., 2022). This choice is particularly natural for variable-frequency converters, because the switching period is already nonuniform in physical time; a fixed-rate sampled-data description would therefore be misaligned with the actuation mechanism.

A second defining feature is single-cycle causality. The sampled variables are not arbitrary waveform samples; they are chosen to match the converter’s switching-cycle logic. For the current-mode buck converter with constant on-time, the sampled output voltage is $v[n]$ and the switching-cycle current variable is the valley current $i_v[n]$. For the current-mode boost converter with constant off-time, the sampled output voltage is again $v[n]$, while the switching-cycle current variable is the peak current $i_p[n]$ (Cui et al., 2022). In the later series-capacitor buck application, the sampled variables are the output voltage $v[n]$, the master-phase current $i_{L1}[n]$, and the follower-phase current $i_{L2}[n]$, all indexed at comparator-triggered switching events (Qian et al., 14 Jul 2025).

A third characteristic is that 5S is control-oriented rather than merely descriptive. The framework is used to derive low-order discrete-time plants for direct digital design, including $z$-domain transfer functions, pole-zero interpretations, and root-locus-based controller tuning (Cui et al., 2022). In the series-capacitor buck case, the same 5S model serves as the small-signal component of an integrated architecture that combines a high-bandwidth digital PI regulator with a large-signal controller based on Pontryagin’s Maximum Principle (PMP) (Qian et al., 14 Jul 2025).

This suggests a useful delimitation. In its explicit power-electronics usage, 5S is not simply any switched state-space model sampled at discrete times. It is a switching-synchronous, event-driven, cycle-to-cycle state-space representation whose sample times coincide with switching-related events and whose state and input definitions are chosen to preserve converter causality.

2. Switching-event synchronization and sampled variables

In 5S, the sampling event is defined by converter timing rather than by an external periodic scheduler. For the constant-on-time current-mode buck converter, the sampling instant is

$$t_s[n] = t_v[n-1] + \lambda T_{\text{on}}, \qquad \lambda\in(0,1).$$

For the constant-off-time current-mode boost converter, the sampling instant is

$$t_s[n] = t_p[n-1] + \lambda T_{\text{off}}, \qquad \lambda\in(0,1).$$

In both cases, the sample is taken once per switching cycle and at a prescribed location inside a constant subinterval, which provides deterministic computational time before the next actuation (Cui et al., 2022).

In the two-phase series-capacitor buck converter, the event definition is comparator-driven. When the measured master-phase current $i_v[n]$0 falls below the reference $i_v[n]$1, the comparator output goes high; that event samples the output voltage, updates the controller, updates the reference current, and initiates the next on-time. The cycle is indexed by event times $i_v[n]$2, and the sampled variables are

$i_v[n]$3

with control input

$i_v[n]$4

The switching period is variable because the off-time is state-dependent, and the follower-phase delay depends on the previous switching period (Qian et al., 14 Jul 2025).

System	Sampled variables	Synchronizing event
COT current-mode buck	$i_v[n]$5, $i_v[n]$6	Valley-current-related switching event
COTF current-mode boost	$i_v[n]$7, $i_v[n]$8	Peak-current-related switching event
Two-phase SCB VRM	$i_v[n]$9, $v[n]$0, $v[n]$1, $v[n]$2	Comparator event when $v[n]$3 falls below $v[n]$4

This timing structure differentiates 5S from conventional averaged models. Standard averaged models are most natural when switching frequency is fixed or nearly fixed, duty ratio is the primary modulation variable, the controller is slow relative to the switching cycle, and dynamics can be represented well by averaging over a switching period. The 5S setting weakens those assumptions: variable frequency is intrinsic, sampling is event-driven rather than uniformly time-driven, and interphase delays or switching-sequence constraints can depend directly on prior switching periods (Qian et al., 14 Jul 2025).

3. Mathematical formulation and discrete-time models

The 5S methodology constructs a discrete-time model over one switching cycle by partitioning that cycle into switching subintervals, writing subinterval dynamics, and then eliminating intermediate variables to obtain a cycle-to-cycle map. For the buck converter, the inductor current is approximated as a linear ramp with slopes

$v[n]$5

and the cycle current updates are

$v[n]$6

After quadratic approximation of the capacitor-voltage evolution and linearization about an operating point, the small-signal model becomes

$v[n]$7

which yields the $v[n]$8-domain plant

$v[n]$9

One pole is interpreted as the slow $i_p[n]$0 pole, $i_p[n]$1 as the one-cycle causality delay, and the zero as reflecting subcycle measurement-actuation delay via $i_p[n]$2 (Cui et al., 2022).

For the boost converter, the 5S plant has the same structural form,

$i_p[n]$3

with parameters expressed in terms of normalized time constants $i_p[n]$4, $i_p[n]$5, and $i_p[n]$6. The next on-time is itself reconstructed from the 5S state: $i_p[n]$7 The same paper also derives a switched-affine continuous-time reconstruction map from the discrete 5S trajectory, showing how the sampled sequence determines the off-interval and on-interval state evolution of the physical converter (Cui et al., 2022).

The series-capacitor buck derivation is more explicitly state-space oriented. One switching period from $i_p[n]$8 to $i_p[n]$9 is divided into four subintervals: $v[n]$0, $v[n]$1, $v[n]$2, and $v[n]$3. Intervals 1 and 3 each have fixed duration $v[n]$4; interval 2 is set by the previous cycle; interval 4 is the remaining off-time in the current cycle. Under the assumptions of a large series capacitor and output capacitor and piecewise-linear inductor currents with slopes

$v[n]$5

the cycle-to-cycle current updates are

$v[n]$6

and

$v[n]$7

The output capacitor current is

$v[n]$8

and the paper writes explicit formulas for $v[n]$9, $i_{L1}[n]$0, $i_{L1}[n]$1, and $i_{L1}[n]$2 across the four subintervals (Qian et al., 14 Jul 2025).

After small-signal linearization, the SCB model becomes

$i_{L1}[n]$3

with

$i_{L1}[n]$4

where $i_{L1}[n]$5 and $i_{L1}[n]$6. Using the current-mode identity

$i_{L1}[n]$7

the plant is written in standard discrete-time state-space form with delay state $i_{L1}[n]$8: $i_{L1}[n]$9 The voltage-to-input transfer function is

$i_{L2}[n]$0

and the follower-current transfer function is

$i_{L2}[n]$1

The paper interprets the two poles at $i_{L2}[n]$2 as discrete-time causality and one-cycle interphase delay, and the pole at $i_{L2}[n]$3 as the output-capacitor integrator; one zero lies in the left-half $i_{L2}[n]$4-plane, while the other is a right-half-$i_{L2}[n]$5-plane zero associated with nonminimum-phase behavior in current-mode constant-on-time control (Qian et al., 14 Jul 2025).

4. Control design and implementation consequences

Because 5S produces a discrete-time plant directly in the switching-cycle index, it supports direct digital controller design in the $i_{L2}[n]$6-domain. For the buck converter, the 2022 paper uses a PI controller with a pole at $i_{L2}[n]$7 for zero steady-state error and tunes the zero and gain by root locus. For the boost converter, it uses a switching-synchronized PI controller, denoted $i_{L2}[n]$8,

$i_{L2}[n]$9

and argues that stability in 5S implies stability in physical time through the continuous-time reconstruction map. The same work states a settling-time bound

$z$0

and an overshoot bound

$z$1

thereby relating cycle-indexed transient design to continuous-time performance (Cui et al., 2022).

The experimental and simulation results reported for these 5S-based controllers are framed as evidence that switching-synchronous modeling is not merely a formal convenience. For the buck prototype, a $z$2 mV small-signal step yields a rise time about $z$3 with no overshoot, while a $z$4 V large-signal step to $z$5 V yields a rise time about $z$6 with less than $z$7 overshoot. For the boost prototype, a $z$8 V staircase yields approximately $z$9 rise time per step, and a load step from $$t_s[n] = t_v[n-1] + \lambda T_{\text{on}}, \qquad \lambda\in(0,1).$$0 W to $$t_s[n] = t_v[n-1] + \lambda T_{\text{on}}, \qquad \lambda\in(0,1).$$1 W at $$t_s[n] = t_v[n-1] + \lambda T_{\text{on}}, \qquad \lambda\in(0,1).$$2 V produces maximum voltage deviation $$t_s[n] = t_v[n-1] + \lambda T_{\text{on}}, \qquad \lambda\in(0,1).$$3 V, equal to $$t_s[n] = t_v[n-1] + \lambda T_{\text{on}}, \qquad \lambda\in(0,1).$$4 of $$t_s[n] = t_v[n-1] + \lambda T_{\text{on}}, \qquad \lambda\in(0,1).$$5 V (Cui et al., 2022).

The 2025 SCB work embeds 5S in a broader integrated architecture. Its 5S model is used to derive the small-signal linear discrete-time plant for a high-bandwidth digital PI controller, intended for small disturbances, reference tracking, and modest load perturbations where the nominal switching sequence is preserved. For heavy load steps, the paper switches to a separate large-signal switched-affine model and uses PMP to compute time-optimal switching sequences and dwell times. The transition logic is described qualitatively as: detect heavy load transient, freeze the small-signal controller internal state, add estimated load-step magnitude to the current reference, hold the delay counter at its previous cycle value, retrieve a precomputed optimal switching sequence and dwell times from a LUT, apply that sequence, force comparator output high to reset the sampling event, and then resume normal switching-synchronized small-signal control (Qian et al., 14 Jul 2025).

A notable converter-specific issue arises here. The SCB paper emphasizes series-capacitor oscillation during heavy load steps if the strict switching sequence is not maintained. If both top switches conduct simultaneously, the input can overcharge the series capacitor and require prolonged recovery. The small-signal 5S model does not directly capture this mechanism, because it assumes the series capacitor is large enough to be an ideal voltage source with negligible ripple. The explicit $$t_s[n] = t_v[n-1] + \lambda T_{\text{on}}, \qquad \lambda\in(0,1).$$6 dynamics needed to represent sequence-violation oscillation appear only in the large-signal switched-affine model (Qian et al., 14 Jul 2025). This is a central limitation of 5S in that application: the small-signal event-synchronized model is accurate for nominal-sequence operation, but not sufficient for all large-signal switching anomalies.

5. Relation to broader sampled switched-system research

The term 5S is explicit in the variable-frequency power-converter literature, but several closely related research lines use the same structural ideas without that name. One established line studies sampled switched systems with switching allowed only at fixed periodic instants $$t_s[n] = t_v[n-1] + \lambda T_{\text{on}}, \qquad \lambda\in(0,1).$$7, yielding mode-indexed sampled transition systems $$t_s[n] = t_v[n-1] + \lambda T_{\text{on}}, \qquad \lambda\in(0,1).$$8 and controller synthesis by symbolic abstraction or continuous-state predecessor computation (Fribourg et al., 2011). Another studies sampled switched systems with synchronized mode patterns held constant on intervals $$t_s[n] = t_v[n-1] + \lambda T_{\text{on}}, \qquad \lambda\in(0,1).$$9, semi-Lagrangian gridding, and one-sided Lipschitz Euler error bounds that certify sampled-time and, under additional convexity conditions, dense-time safety (Coënt et al., 2019). A distributed synthesis line treats linear discrete-time switching systems with state-dependent mode selection and region-to-pattern maps over synchronized macro-steps (Coënt et al., 2016). A self-triggered line formulates finite sequences of future sampling intervals as modes of a lifted switched system $$t_s[n] = t_p[n-1] + \lambda T_{\text{off}}, \qquad \lambda\in(0,1).$$0 under synchronous state measurements (Tariverdi, 2 Nov 2025).

These works clarify what is specific and what is generic in 5S. The generic element is the reduction of a continuous or hybrid system to a sampled, mode-dependent state-space model on a synchronized decision grid. The specific 5S element, in the strict sense of the power-electronics papers, is that the synchronization grid itself is induced by switching events and may therefore be nonuniform in physical time. Fixed-period sampled switched systems, pattern-based safety synthesis, and self-triggered sampling-sequence optimization are structurally close, but they do not share the same event-driven converter semantics.

A plausible implication is that 5S can be viewed as one technically specialized branch within a broader family of switching sampled-state-space methods. In that broader family, different works emphasize different aspects: exact or approximate sampled flows (Fribourg et al., 2011), formal safety tubes (Coënt et al., 2019), region-based backward reachability (Coënt et al., 2016), or sampling-pattern optimization under synchronous measurements (Tariverdi, 2 Nov 2025). The 5S literature adds the explicit claim that, for variable-frequency power converters, switching-event synchronization is the natural coordinate system for both modeling and digital control.

6. Limitations, misconceptions, and extensions

A common misconception is to equate 5S with any discrete-time switched model. The literature does not support that equivalence. In the strict usage where the term is introduced and reused, 5S is tied to switching-synchronized sampling events, single-cycle control updates, and discrete models indexed by switching cycles rather than by a fixed-rate external clock (Cui et al., 2022). Related sampled switched-system papers may be conceptually close, but they are not automatically 5S in the terminological sense.

Another misconception is that 5S eliminates the need for hybrid or large-signal models. The SCB example shows the opposite. The small-signal 5S derivation assumes large $$t_s[n] = t_p[n-1] + \lambda T_{\text{off}}, \qquad \lambda\in(0,1).$$1 and $$t_s[n] = t_p[n-1] + \lambda T_{\text{off}}, \qquad \lambda\in(0,1).$$2 so their ripple can be neglected, fixed linear current slopes $$t_s[n] = t_p[n-1] + \lambda T_{\text{off}}, \qquad \lambda\in(0,1).$$3, identical phase inductances, and nominal strict switching sequence. It does not describe arbitrary switching overlap or sequence violations; those cases are handled later by a separate switched-affine large-signal model for PMP (Qian et al., 14 Jul 2025). Likewise, the 2022 derivations rely on continuous-conduction-mode operation, small output ripple, piecewise-linear inductor current, and constant on-time or constant off-time within each cycle (Cui et al., 2022).

A further limitation is that 5S is not intrinsically a formal safety framework. The converter papers use it for control-oriented modeling and high-speed digital design, not for correct-by-design safety certificates. By contrast, other sampled switched-system methods explicitly synthesize controls that keep exact trajectories inside a safety set for a finite or iterated horizon, using gridding, dynamic programming, and verified error radii (Coënt et al., 2019). This suggests that 5S and formal safe-control techniques are complementary rather than interchangeable.

The framework nevertheless admits meaningful extensions. The SCB paper already expands 5S from single-phase current-mode buck and boost converters to a variable-frequency two-phase series-capacitor buck VRM with one-cycle interphase delay, RHZP zero, and integrated small-signal/large-signal control (Qian et al., 14 Jul 2025). The broader sampled switched-system literature suggests further directions: state-dependent region-to-pattern control (Coënt et al., 2016), synchronous-measurement sequence scheduling (Tariverdi, 2 Nov 2025), and explicit safety certification over sampled mode patterns (Coënt et al., 2019). This suggests that 5S is best understood not as a closed doctrine, but as a precise event-synchronized sampled-state-space methodology whose core utility lies in modeling systems according to their actual switching logic rather than according to an externally imposed uniform sampling clock.