Subcircuit Volumetric Benchmarking (SVB)

Updated 11 August 2025

Subcircuit Volumetric Benchmarking (SVB) is a scalable method that extracts representative subcircuits from large compiled circuits to quantify process fidelity per quantum operation.
The methodology employs mirror circuit fidelity estimation and geometric mean aggregation to derive effective error metrics over circuit width and depth.
SVB informs hardware progress and digital accelerator design by linking subcircuit performance metrics to overall system capability and noise model validation.

Subcircuit Volumetric Benchmarking (SVB) is a scalable methodology for benchmarking quantum devices and algorithms, designed to quantify the ability of near-term quantum computers to perform large-scale, application-relevant computations. SVB extends traditional volumetric benchmarking by extracting representative subcircuits—fragments with specified width and depth—directly from compiled target circuits that may be orders of magnitude too large for current hardware. By measuring the process fidelity of these subcircuits and aggregating results through well-defined metrics, SVB enables both fine-grained and system-level assessments of hardware progress toward utility-scale quantum algorithms (Seritan et al., 7 Aug 2025). SVB has also found analogues in digital computing-in-memory accelerator design, where subcircuit-level metrics inform architectural synthesis (Shao et al., 25 Nov 2024). The methodology is closely related to generalized benchmarking techniques that consider higher-dimensional circuit features, as well as to context-aware gate and noise model benchmarking (Proctor et al., 17 Apr 2025, Cirstoiu et al., 2022, Debroy et al., 2023, Weber et al., 2023).

1. Core Principles and Formal Definition

SVB is premised on the idea that the reliable execution of a “full” quantum algorithm is rarely accessible on contemporary hardware, but that sampling and benchmarking its “snipped” subcircuits can yield scalable, context-rich, and application-targeted insight. The protocol is formally defined as follows:

Target circuit and “snipping”: Given a target circuit $c$ fully compiled to device connectivity and gate set, subcircuits (“snippets”) of specified width $w$ (number of qubits) and depth $d$ (number of layers) are extracted by selecting a starting layer and a connected subset of qubits, ensuring the subcircuit mirrors typical hardware allocation and temporal structure.
Subcircuit fidelity estimation: For each subcircuit $c_{w,d,j}$ (with $j$ indexing samples of identical shape), a process fidelity $F(c_{w,d,j})$ is estimated using mirror circuit fidelity estimation (MCFE) or equivalent scalable protocols. The geometric mean, $\text{GM}[F_{w,d}]$ , serves as an aggregate estimate for each shape.
Effective error per quop: The primary error metric is

$\varepsilon_{w,d} = 1 - (\text{GM}[F_{w,d}])^{\frac{1}{w \cdot d}},$

which interprets the geometric average per quantum operation.

Capability coefficient and system capability: Extrapolating over all $w$ and $d$ attainable, one defines the effective number of quops $Q_{w,d} = 1/\varepsilon_{w,d}$ , and, for a target circuit of shape $(w_c, d_c)$ , an extrapolated full-circuit fidelity

$\hat{F}_c = (1 - \varepsilon_{w,d})^{w_c d_c}.$

The capability coefficient is then $Q_C / Q_T$ , with $Q_T = w_c d_c$ and $Q_C = 1/\varepsilon_{w_\text{max}}$ .

SVB thereby parameterizes device performance not as a single number, but as a function over the $(w,d)$ plane or higher-dimensional feature space (Seritan et al., 7 Aug 2025, Proctor et al., 17 Apr 2025).

2. Methodological Foundations and Protocol Steps

The SVB protocol is implemented through the following methodological steps:

Selection of Subcircuits: For each desired $(w,d)$ , uniformly sample a starting layer, select a random $n'$ -qubit subset reflecting available hardware ( $n' < n$ if $n$ is the full device size), and extract a connected set of $w$ qubits. Retain all operations among these $w$ within the $d$ chosen layers, discarding gates connecting outside.
Fidelity Measurement: Employ MCFE or direct process fidelity estimation. The process fidelity is mathematically expressed as:

$F = \langle \Psi | (\mathbb{I} \otimes \mathcal{E})[|\Psi\rangle\langle\Psi|] | \Psi \rangle,$

where $\mathcal{E}$ is the noisy quantum channel estimated by comparing device implementation to the ideal evolution $U$ .

Data Aggregation: For each $(w,d)$ , collect $K$ independent samples, compute geometric mean fidelities, and deduce $\varepsilon_{w,d}$ .
Extrapolation: Estimate the fidelity and effective “quops” for the target circuit. Benchmark device capability by comparing “predicted” (from narrow, e.g., $w=2$ snippets) versus “observed” (from wide, $w=w_{\text{max}}$ snippets) system capacities.

This structure enables benchmarking across a continuous range of widths and depths within the operational margin of the device (Seritan et al., 7 Aug 2025).

3. Metrics, Performance Summaries, and Capability Regions

SVB formalizes several key metrics:

Metric	Symbol/Formula	Interpretation
Process fidelity	$F$	Quality of subcircuit implementation
Effective error per quop	$\varepsilon_{w,d} = 1 - (\text{GM}[F_{w,d}])^{1/(w d)}$	Mean infidelity per quantum operation
Effective capability (in quops)	$Q_{w,d} = 1/\varepsilon_{w,d}$	Maximal number of quops at given shape
Full-circuit extrapolated fidelity	$\hat{F}_c = (1 - \varepsilon_{w,d})^{w_c d_c}$	Projected fidelity for complete target circuit
Capability coefficient	$Q_C / Q_T$	Fraction of target computation reliably executable

Performance summaries are visualized volumetrically—across the $(w,d)$ grid—revealing the capability region for the hardware. These regions compactly summarize, for each width and depth, the expected process fidelity and effective operational “volume.” In generalized frameworks, such as featuremetric benchmarking, additional circuit features (two-qubit gate density, problem parameters) can be incorporated, and Gaussian process regression is employed to interpolate and smooth the resultant capability landscape (Proctor et al., 17 Apr 2025).

4. Applications, Experimental Results, and Comparative Perspective

SVB was demonstrated on IBM Q systems, benchmarking subroutines from quantum chemistry simulations (Hamiltonian block encoding with Jordan–Wigner and Bravyi–Kitaev mappings). Key findings include:

Context dependence: Effective error per quop increases significantly with snippet width, evidencing crosstalk, correlated noise, and other non-Markovian processes. Extrapolations from narrow subcircuits (e.g., $w=2$ ) overestimate system capability compared to wider ones (Seritan et al., 7 Aug 2025).
Fidelity gap: The observed system capability in “quops” on present devices (e.g., IBM Q systems in 2022–2024) was a small fraction (as low as 0.03% to 5%) of what would be required to execute end-to-end target circuits for practical application.
Application to benchmarking toolchains: Modular software frameworks such as Qermit (Cirstoiu et al., 2022)—built as graph-based compositions of error mitigation and estimation tasks—facilitate rapid prototyping of benchmarking experiments that use SVB or related volumetric metrics.

SVB directly contrasts with conventional approaches that rely on either random circuit benchmarking (which may not mirror algorithmic context or scale) or full-circuit fidelity estimation (intractable for large targets). It is further generalizable to future logical qubit systems as error correction becomes practical, and its structure admits integration with advanced data analysis tools (e.g., Gaussian process models) (Proctor et al., 17 Apr 2025).

Recent research situates SVB within a broader benchmarking paradigm:

Featuremetric Benchmarking: SVB is a special case ( $\chi=2$ , features = width and depth) of featuremetric benchmarking, which allows inclusion of additional features (e.g., two-qubit gate density, active qubit sets). Performance is then summarized as a smooth, multidimensional capability function $s(\vec{v})$ , often learned via Gaussian process regression (Proctor et al., 17 Apr 2025). This generalization allows more predictive and application-specific assessment.
Context-aware fidelity estimation (CAFE): Frameworks such as CAFE repeat subcircuits inside experiments to expose spatial and temporal error context, separating coherent and incoherent errors. This provides subcircuit-level error budgets complementary to SVB’s volumetric fidelity mapping (Debroy et al., 2023).
Noise model benchmarking: SVB-like approaches also underpin systematic evaluation of calibrated noise models. Here, circuit distributions over subcircuit regimes $(w, d)$ are compared between hardware and noise model simulations, with errors quantified via metrics such as Hellinger distance or absolute deviation in observable means. This aids both model validation and selection of error mitigation strategies (Weber et al., 2023).
Digital compute-in-memory benchmarking: In digital in-memory accelerators, “subcircuit volumetric benchmarking” refers to the synthesis and aggregated performance evaluation of fundamental subcircuits within flexible design libraries, with optimization criteria for throughput, area, and power encoded in parametric, volumetric fashion (Shao et al., 25 Nov 2024).

6. Practical Implications and Limitations

SVB offers critical advantages for assessing technological readiness:

Scalability: By benchmarking at the subcircuit level, SVB allows robust extrapolation to utility-scale circuits without suffering the exponential overheads of full classical simulation or output probability estimation.
Context fidelity: SVB captures genuine device error in relevant circuit context—accounting for interactions, connectivity, and algorithmic structure omitted by generic benchmarks.
System design integration: Capability coefficients provide a transparent, quantitative measure for comparing devices, compilation strategies, and error mitigation protocols, as well as evaluating technological progression year-on-year (Seritan et al., 7 Aug 2025, Cirstoiu et al., 2022).

However, SVB relies on the assumption that performance of typical subcircuits is predictive (via geometric mean process fidelity) of full-circuit behavior, which may break down if rare pathological error patterns or strong error correlations are present. A plausible implication is that future SVB protocols may incorporate even more sophisticated context sampling or higher-dimensional feature analysis to address these limitations.

In summary, Subcircuit Volumetric Benchmarking constitutes a central methodology for evaluating and projecting quantum processor performance toward practical, large-scale quantum computation. Its adoption and ongoing development highlight the move from abstract, small-scale benchmarks to ones fully embedded in the structure and demands of quantum algorithms and real-world applications.