Stairway Codes: An Overview

• Stairway codes are high-rate, product-like block-convolutional error-correction codes defined by staircase-shaped coupling and iterative bounded-distance decoding.
• They enable high-speed optical transport by integrating algebraic component decoding with sliding-window processing to achieve low internal dataflow and reduced implementation complexity.
• Variants such as generalized staircase, feed-forward, and secret-sharing adaptations balance error floor, decoding performance, and system constraints across communication and storage applications.

“Stairway codes” is an informal label most often applied to staircase codes: high-rate, product-like, block-convolutional forward-error-correction codes in which an infinite sequence of blocks is coupled by staircase-shaped component-code constraints, originally developed for very high-speed optical transport and related links (Smith et al., 2012). In current coding theory, the standardized term is usually staircase code rather than stairway code; however, the same staircase metaphor has also been used for broader spatially coupled product-like families, for communication-efficient secret sharing, and for storage-system erasure coding, so the term is context-sensitive (Shehadeh et al., 2023).

1. Terminology, scope, and historical placement

In the optical-FEC literature, staircase codes were introduced as a hard-decision alternative to high-complexity soft-decision schemes for 100 Gb/s optical transport networks, combining algebraic component decoding with a streaming, convolutional-style coupling between successive blocks (Smith et al., 2012). The phrase “stairway code” is not the canonical name in that literature; it is better understood as an informal synonym for staircase codes and, by extension, for several staircase-shaped generalizations (Shehadeh et al., 2023).

This usage should be distinguished from two separate naming conventions. In distributed storage, STAIR codes are erasure codes for tolerating both device and sector failures; despite the visual metaphor, they are not optical staircase codes and are built from systematic MDS row and column codes rather than from spatially coupled BCH-style component constraints (Li et al., 2014). In secret sharing, staircase codes denote linear communication-efficient secret-sharing schemes over $GF(q)$, again unrelated to optical staircase FEC except for the matrix pattern that motivates the name (Bitar et al., 2015).

Within the optical and product-like coding lineage, staircase codes sit alongside braided block codes, zipper codes, tiled diagonal zipper codes, continuously interleaved codes, and more recent generalized or higher-order staircase constructions. This suggests that “stairway code” is best treated as a family resemblance term rather than a uniquely standardized taxonomy.

2. Classical staircase codes

The classical staircase code is defined by an infinite sequence of binary blocks

$B_0, B_1, B_2, \ldots$

with each $B_i$ an $m\times m$ matrix and $B_0$ fixed to a known reference, typically the all-zero matrix. A binary linear component code $C$ of length $2m$ is chosen, and the defining constraint is that for every $i\ge 1$, each row of

$[B_{i-1}^{T}\; B_i]$

is a codeword of $C$ (Smith et al., 2012). In the equivalent formulation used in later work, the current block is coupled to the previous block through the transpose operation, giving the familiar staircase geometry in time (Shehadeh et al., 2023).

Each bit participates in exactly two component codewords: one through the current block and one through the neighboring coupled block. This degree-2 participation is a defining structural property of the classical construction. If the component code has length $B_0, B_1, B_2, \ldots$0 and dimension $B_0, B_1, B_2, \ldots$1, the asymptotic staircase-code rate can be written as

$B_0, B_1, B_2, \ldots$2

or, in the equivalent row/parity-column parameterization, $B_0, B_1, B_2, \ldots$3 (Häger et al., 2017, Smith et al., 2012).

For 100 Gb/s OTN, Smith et al. proposed a G.709-compatible staircase code with rate $B_0, B_1, B_2, \ldots$4, using $B_0, B_1, B_2, \ldots$5 and $B_0, B_1, B_2, \ldots$6, together with a shortened length-1022 BCH component code derived from a binary $B_0, B_1, B_2, \ldots$7 BCH code augmented by the factor $B_0, B_1, B_2, \ldots$8 (Smith et al., 2012). The reported performance was a net coding gain of $B_0, B_1, B_2, \ldots$9 dB at output BER $B_i$0, $B_i$1 dB better than the best code from ITU-T G.975.1, and an estimated error floor of $B_i$2 (Smith et al., 2012). These figures established staircase codes as a reference architecture for high-throughput hard-decision FEC in optical transport.

3. Decoding architecture and implementation

Classical staircase decoding is iterative bounded-distance decoding of short algebraic component codes inside a sliding window of consecutive blocks. At each window position, component codewords are decoded in sequence, corrections are fed back into overlapping codewords, and after a fixed number of global iterations the oldest block is released and the window advances (Smith et al., 2012). The decoding is naturally expressed in the syndrome domain, which is central to the hardware appeal of staircase codes.

The implementation argument is not merely qualitative. For the 100 Gb/s setting analyzed by Smith et al., a conventional LDPC decoder with $B_i$3, $B_i$4, and average degree $B_i$5 was estimated to require internal dataflow on the order of $B_i$6 Tb/s, whereas a product-like syndrome-domain decoder was estimated at $B_i$7 Gb/s, with BCH decoding tables adding about $B_i$8 Gb/s (Smith et al., 2012). This low internal dataflow, together with regular memory access and short algebraic component decoders, explains why staircase codes became closely associated with high-speed ASIC/FPGA realization.

A persistent difficulty is miscorrection: bounded-distance decoding may output an incorrect component codeword when the true error pattern lies outside the decoding radius but another codeword lies within it. Several decoder refinements therefore target miscorrection suppression or limited soft assistance while preserving the hard-decision architecture.

Decoder variant	Core mechanism	Reported effect
“Miscorrection-free Decoding of Staircase Codes” (Häger et al., 2017)	Anchors, frozen codewords, backtracking, reduced capability at the newest position	About $B_i$9 dB gain at BER $m\times m$0; error floor reduced by over an order of magnitude
“Decoding Staircase Codes with Marked Bits” (Lei et al., 2018)	Highly reliable / highly unreliable bit marking for miscorrection detection and bit flipping	Up to $m\times m$1 dB at BER $m\times m$2
“Improved Decoding of Staircase Codes: The Soft-aided Bit-marking (SABM) Algorithm” (Lei et al., 2019)	HRB/HUB marking, miscorrection detection, targeted bit flipping	Up to $m\times m$3 dB at BER $m\times m$4; relative complexity increase only around $m\times m$5 at BER $m\times m$6
“A Soft-Aided Staircase Decoder Using Three-Level Channel Reliabilities” (Lei et al., 2021)	Three-level reliabilities, random HUB selection, multi-block soft-aiding	Up to $m\times m$7 dB over SABM and $m\times m$8 dB over standard SCC decoding at BER $m\times m$9
“Decoding Product Codes and Staircase Codes with Iteration-Independent Weighting Coefficients” (Straßhofer, 13 May 2026)	Log-domain list-based soft output with fixed iteration-independent $B_0$0	$B_0$1 dB gain for staircase codes and $B_0$2 dB for product codes at BER $B_0$3

Taken together, these results show that staircase decoding has evolved along two complementary lines: structurally aware hard-decision control of miscorrections, and low-resolution or list-based soft assistance that avoids the full complexity of soft-decision message passing.

4. Generalized bit degree and unified staircase-like frameworks

A major limitation of the classical code is the fixed bit degree 2. Generalized staircase codes remove this restriction by allowing each bit to participate in $B_0$4 component codewords rather than exactly two. The defining constraint becomes

$B_0$5

with each row required to belong to a component code $B_0$6 of length $B_0$7, where the $B_0$8 are permutations and the offsets $B_0$9 form a ruler (Shehadeh et al., 2023). Classical staircase codes are recovered by the special case $C$0, $C$1, $C$2, and $C$3 (Shehadeh et al., 2023).

The construction is constrained by an intersection property: distinct component codewords should intersect in at most one bit. To obtain it, the ruler is chosen as a Golomb ruler, and the permutations are required to form an $C$4-net. Under iterative bounded-distance decoding with component capability $C$5, this guarantees that the lowest weight of an uncorrectable error pattern is at least

$C$6

(Shehadeh et al., 2023). This is the main theoretical reason higher bit degree can suppress error floors even when each component decoder is very weak.

The 2023 generalized staircase paper emphasizes extended Hamming components with $C$7, using many simple decoders instead of fewer strong BCH decoders. It reports error floors below $C$8 for almost all simulated configurations, with at least $C$9 bits simulated without error at the lowest operating point, while performing roughly $2m$0 to $2m$1 dB worse than designs using two triple-error-correcting BCH components per bit as code overhead ranges from $2m$2 to $2m$3 (Shehadeh et al., 2023). The stated motivation is reduced power consumption, since BCH decoder power is described as roughly proportional to $2m$4.

A broader unification appears in higher-order staircase codes, parameterized by $2m$5 and constructed from difference triangle sets and finite-geometric nets. These codes have rate

$2m$6

bit degree $2m$7, and include classical staircase codes, generalized staircase codes, tiled diagonal zipper codes, OFEC codes, multiply-chained TDZC, Robinson–Bernstein recurrent codes, and continuously interleaved codes as special cases (Shehadeh et al., 2024). Their memory requirements are controlled by the DTS scope, and the paper explicitly studies minimum-scope designs as memory-optimal higher-order staircase codes (Shehadeh et al., 2024).

A related abstraction is given by zipper codes, which treat staircase and braided block codes as members of a common spatially coupled product-like framework described by virtual/real positions and an interleaver map $2m$8. Under a bijective scattering interleaver, the zipper-code analysis proves that any stall pattern for a $2m$9-error-correcting constituent code has at least

$i\ge 1$0

errors (Sukmadji et al., 2022). This does not replace staircase-specific analysis, but it provides a graph-theoretic language for comparing staircase, diagonal, delayed-diagonal, and tiled couplings.

5. Variants motivated by termination, block size, and deployment constraints

The original staircase encoder is recursive: parity bits in one block influence future parity bits, leading to parity propagation. Feed-forward staircase codes were introduced to remove this behavior and to provide a systematic way of terminating a staircase code after an arbitrary number of blocks. The construction uses a self-protection technique so that parity does not propagate indefinitely; the related partial feed-forward staircase code allows parity propagation over a given number of blocks, amortizes the self-protection complexity, and has the same error-floor as staircase codes (Zhang et al., 2016). Simulations reported that both feed-forward and partial feed-forward variants have waterfall and error-floor performance similar to original staircase codes (Zhang et al., 2016).

A different deployment constraint is block granularity. Sub-block rearranged staircase codes decompose preceding blocks into sub-blocks, transpose and rearrange them, and thereby produce each transmitted block at size $i\ge 1$1 of a conventional staircase block while retaining the same rate and component codes (Qiu et al., 2022). This permits the use of stronger algebraic component codes to obtain codes with similar or identical effective block size and rate as weaker classical staircase designs. The paper further reports that larger coupling width improves both waterfall and error-floor performance, supported by density evolution, error-floor analysis, and simulation (Qiu et al., 2022).

These variants illustrate a recurrent design pattern in the staircase literature. The core staircase constraint is preserved, but the engineering objectives change: one line of work targets lower power through weak component decoders and higher bit degree, another targets clean termination, another targets smaller transmitted blocks or stronger components at fixed rate, and yet another targets better soft-output behavior without abandoning sliding-window architectures. This suggests that the staircase paradigm is less a single code than a structured design space for balancing component strength, coupling memory, error floor, and implementation cost.

6. Distinct staircase-inspired code families outside optical FEC

The most common misconception is that every “stair” or “staircase” code belongs to the optical hard-decision lineage. Two important exceptions are separate subjects.

First, STAIR codes in storage systems are erasure codes for tolerating both device failures and sector failures. They assume an $i\ge 1$2 stripe, tolerate up to $i\ge 1$3 device failures plus a configurable vector of sector failures

$i\ge 1$4

and use two systematic MDS codes: a row code $i\ge 1$5 and a column code $i\ge 1$6 (Li et al., 2014). Their characteristic constructions are upstairs encoding and downstairs encoding, chosen according to configuration-dependent encoding cost. They are not spatially coupled BCH-based staircase codes; they are storage erasure codes whose “stair” refers to the parity layout and failure pattern geometry (Li et al., 2014).

Second, staircase codes for communication-efficient secret sharing are linear schemes over $i\ge 1$7, $i\ge 1$8, for threshold secret sharing with privacy against $i\ge 1$9 colluding parties and reconstruction threshold $[B_{i-1}^{T}\; B_i]$0. Their central optimality statement is that when a legitimate user contacts $[B_{i-1}^{T}\; B_i]$1 parties, the communication and read overheads satisfy

$[B_{i-1}^{T}\; B_i]$2

which matches the information-theoretic lower bound (Bitar et al., 2015). These codes are explicit matrix constructions based on Vandermonde encoding and a staircase-structured placement of secret symbols and random keys; the staircase shape is algebraic rather than convolutional (Bitar et al., 2015).

Accordingly, “stairway code” has no single universal technical meaning. In optical communications, it ordinarily denotes staircase codes and their block-convolutional generalizations; in storage, it may denote STAIR codes; in secret sharing, it may denote a different staircase-structured linear code. For coding theorists and system designers, the decisive distinction is therefore not the metaphorical name but the underlying model: spatially coupled hard-decision FEC, storage erasure protection, or communication-efficient secret sharing.