Staircase Decoding in Optical Communications

• Staircase decoding is a syndrome-domain, bounded-distance iterative approach that processes overlapping block constraints to efficiently correct errors in optical communications.
• The method alternates between horizontal and vertical component-code decoding while integrating miscorrection suppression and reliability-based bit marking to lower error floors.
• Structural generalizations and hybrid soft-aided decoders expand its scope, enabling applications with polar and product codes while balancing performance and computational complexity.

Staircase decoding is best understood as an instance of syndrome-domain, bounded-distance, iterative decoding performed over a sliding window of received blocks. In the classical bit-degree-$2$ case, each bit is protected by exactly two component codewords—one “horizontal” constraint and one “vertical” constraint—and the decoder alternates between these two families of constraints, passing hard decisions, or in some variants limited soft information, until convergence or a fixed iteration limit is reached (Shehadeh et al., 2023). In 2012, staircase codes were introduced as forward-error-correction suitable for high-speed optical communications, and an ITU-T G.709-compatible staircase code with rate $R=239/255$ was reported to achieve a net coding gain of $9.41$ dB at output BER $10^{-15}$, with an error floor at $4.0\times 10^{-21}$ (Smith et al., 2012).

1. Canonical decoding model

Classical staircase codes are defined on an infinite sequence of binary blocks $B_0,B_1,\dots$, with $B_0$ initialized to all zero. For an extended binary BCH component code $\mathcal C$ with parameters $(n_c,k_c,t)$, minimum distance $d_0\ge 2t+2$, the staircase blocks are $R=239/255$0 matrices with $R=239/255$1, and each row of $R=239/255$2 is a codeword in $R=239/255$3. In this notation the code rate is $R=239/255$4, where $R=239/255$5 (Lei et al., 2018).

The decoding window contains a fixed number of consecutive blocks. Iterative decoding then applies bounded-distance decoding (BDD) to all component codewords inside that window, with any accepted flips immediately reflected in adjacent component words. Published schedules differ in traversal order but preserve the same principle. One description alternates between all “horizontal” component codewords formed by $R=239/255$6 and all “vertical” component codewords formed by $R=239/255$7, stopping when no component decoder makes any flips or when a fixed maximum number of iterations is reached, often $R=239/255$8–$R=239/255$9 (Shehadeh et al., 2023). Another description performs a backward pass over row-wise component codewords and then a forward pass over the transpose direction, updating adjacent syndromes after each corrected flip (Smith et al., 2012).

This baseline decoder is a hard-decision message-passing architecture: component decoders exchange only bit flips or corrected hard decisions, not full posterior distributions. That restriction is the source of the architecture’s very low internal data flow, but it also makes the decoder sensitive to failures and miscorrections.

2. Bounded-distance decoding, miscorrections, and stall patterns

For a received length-$9.41$0 vector $9.41$1, BDD has three canonical outcomes. It succeeds if there exists a unique codeword $9.41$2 with $9.41$3, fails if all codewords are farther than $9.41$4, and miscorrects if it outputs some $9.41$5 with $9.41$6, even though that output is undesired (Lei et al., 2018). In staircase decoding, miscorrections are particularly damaging because they are injected back into neighboring component constraints and can propagate across the window.

One response that remains entirely in the hard-decision and syndrome domain is anchor-based miscorrection suppression. In the miscorrection-free decoder, a set of trusted “anchor” codewords is maintained together with frozen codewords and conflict associations. A newly decoded component is frozen if its proposed flips conflict with an anchor whose conflict count is still below threshold $9.41$7, whereas anchors with too many conflicts are backtracked. The paper uses $9.41$8 and also reduces the error-correcting radius from $9.41$9 to $10^{-15}$0 for newly entering edge codewords. For the example with $10^{-15}$1, $10^{-15}$2, $10^{-15}$3, $10^{-15}$4, and $10^{-15}$5, the proposed algorithm recovers virtually all of the $10^{-15}$6 dB gap between conventional and idealized decoding at post-FEC BER $10^{-15}$7, matching the idealized curve down to BERs below $10^{-15}$8, and reduces the error floor by more than an order of magnitude (Häger et al., 2017).

The residual error floor is commonly described in terms of stall patterns. A $10^{-15}$9 stall pattern is a set of bit-errors supported on $4.0\times 10^{-21}$0 rows and $4.0\times 10^{-21}$1 columns such that every involved row and every involved column contains at least $4.0\times 10^{-21}$2 errors. The minimal case is $4.0\times 10^{-21}$3, with $4.0\times 10^{-21}$4. A low-complexity stall-resolution method forms a mask from the intersection of nonzero row- and column-syndrome indicators and flips the corresponding bits; this provably resolves all minimal $4.0\times 10^{-21}$5 stall patterns. For a code with $4.0\times 10^{-21}$6, $4.0\times 10^{-21}$7, $4.0\times 10^{-21}$8, and rate $4.0\times 10^{-21}$9, the predicted error floor drops from about $B_0,B_1,\dots$0 to about $B_0,B_1,\dots$1 (Holzbaur et al., 2017). In the earlier G.709-compatible $B_0,B_1,\dots$2 design, minimal stalls have exactly $B_0,B_1,\dots$3 rows $B_0,B_1,\dots$4 columns, hence $B_0,B_1,\dots$5, and the union-bound analysis yields an error floor of approximately $B_0,B_1,\dots$6 (Smith et al., 2012).

3. Reliability-aided hard-decision decoding

A major line of work preserves the staircase decoder’s algebraic BDD core but augments its outer decisions with a small amount of soft information. In the marked-bit decoder, the receiver computes per-bit LLRs

$B_0,B_1,\dots$7

uses $B_0,B_1,\dots$8 as a reliability measure, marks bits with $B_0,B_1,\dots$9 as highly reliable bits (HRBs), and among the remaining bits in the last block or blocks selects the $B_0$0 or fewer least reliable as highly unreliable bits (HUBs). Miscorrection detection is triggered if the BDD flips would conflict with a zero-syndrome codeword in the previous block or if any flipped bit in the newest block is an HRB. Bit flipping is then applied in two cases: after BDD failure, the decoder flips the single least reliable HUB; after detected miscorrection, it computes $B_0$1 and flips the $B_0$2 least reliable HUBs before rerunning BDD. The BCH decoder internals are unchanged, and the soft-information memory is restricted to the last two blocks in the window (Lei et al., 2018).

For staircase codes with $B_0$3-error-correcting BCH component codes, this soft-aided bit-marking algorithm improves upon standard SCC decoding by up to $B_0$4 dB at BER $B_0$5, while an idealized genie-aided bound gives $B_0$6 dB. The same work reports a relative complexity increase of only around $B_0$7 at BER $B_0$8, decreasing as the channel improves, and extends the method to product codes, where gains of up to $B_0$9 dB at BER $\mathcal C$0 are reported (Lei et al., 2019).

The improved SABM decoder generalizes the marking into three reliability levels. A bit is marked as HRB if $\mathcal C$1, as uncertain if $\mathcal C$2, and as HUB if $\mathcal C$3. The decoder applies the soft-aided procedure to multiple SCC blocks, classifies HUBs by threshold rather than sorting, and randomly selects the HUBs to be flipped. For BCH$\mathcal C$4-based SCCs, gains of up to $\mathcal C$5 dB with respect to SABM and $\mathcal C$6 dB with respect to standard SCC decoding at BER $\mathcal C$7 are reported; with $\mathcal C$8-bit reliability marking, the gain penalty is up to $\mathcal C$9 dB together with a significantly reduced memory requirement (Lei et al., 2021).

A later parameter-optimization study emphasizes that the marking thresholds and the number of modified component decodings heavily affect the performance of iSABM-SCC. With optimized thresholds and decoding counts, the gap to the achievable information rates of hard-decision codes is reduced to $(n_c,k_c,t)$0–$(n_c,k_c,t)$1 dB for code rates $(n_c,k_c,t)$2–$(n_c,k_c,t)$3 in AWGN with $(n_c,k_c,t)$4-ary pulse amplitude modulation, and the obtained reach increase is up to $(n_c,k_c,t)$5 for data rates between $(n_c,k_c,t)$6 Gbps and $(n_c,k_c,t)$7 Gbps in an optical fiber channel (Lei et al., 2021).

4. Ternary, error-and-erasure, and hybrid decoders

Another family of staircase decoders replaces the binary hard-decision front end by a ternary quantizer with outputs $(n_c,k_c,t)$8, where the third symbol denotes an erasure. On a BI-AWGN channel, the quantizer uses symmetric thresholds $(n_c,k_c,t)$9, and the component decoder performs classical error-and-erasure decoding or its simplified form EaED$d_0\ge 2t+2$0, which corrects patterns satisfying a combined errors-and-erasures condition. Density evolution is then carried out with two state variables, the error probability and the erasure probability of VN-to-CN messages. The resulting analysis can optimize both component-code configurations and channel quantizer levels, and Monte Carlo simulations show that additional coding gains of up to $d_0\ge 2t+2$1 dB are possible at only a small additional increase in complexity compared to traditional binary message passing (Rapp et al., 2021).

Full extrinsic message passing (EMP) on the error-and-erasure channel is substantially more expensive than intrinsic message passing, because a naive implementation would require one extrinsic component decode per bit. A simplified EMP construction derives the extrinsic outputs from a single intrinsic decode plus logical distance updates that exploit the algebraic structure of the component code and the EaE rule. In the heuristic h-LCEA version, the average number of BDD steps is exactly one per row or column, and for a $d_0\ge 2t+2$2 staircase code after $d_0\ge 2t+2$3 half-iterations the reported gain is about $d_0\ge 2t+2$4 dB relative to iBDD-IMP, with up to $d_0\ge 2t+2$5 dB improvement compared to standard EMP decoding (Miao et al., 2022).

The BEE-SCC decoder combines reliability weighting with a second decoding attempt based on error-and-erasure decoding. One branch performs iBDD-CR, combining BDD outputs with channel LLRs through an optimized LUT and then hard-deciding; the second branch marks the two least reliable positions as erasures, performs algebraic EED, and compares the two candidate outputs by a generalized-distance score. Only binary messages and a failure flag are exchanged between component decoders. For SCCs based on eBCH $d_0\ge 2t+2$6 with $d_0\ge 2t+2$7-QAM, BEE-SCC achieves a gain of $d_0\ge 2t+2$8 dB over iBDD and $d_0\ge 2t+2$9 dB over iBDD-CR at BER $R=239/255$00, corresponding to a $R=239/255$01 optical-reach increase over iBDD with bit-interleaved coded modulation using $R=239/255$02 quadrature amplitude modulation (Sheikh et al., 2020).

A more recent soft-aided hard-decision decoder, DRSD, uses an erasure threshold on the channel magnitude, a small integer dynamic reliability score $R=239/255$03 per bit, and an anchor threshold schedule $R=239/255$04 for all but the oldest block in a window. Each component word is decoded by an error-and-erasure decoder with candidate rejection based on “anchor bits,” and the reliability scores are incremented or decremented according to whether a bit was stable or flipped. For a rate-$R=239/255$05 staircase code with shortened $R=239/255$06 BCH components, $R=239/255$07, and $R=239/255$08, DRSD requires $R=239/255$09 dB at BER $R=239/255$10, compared with $R=239/255$11 dB for iBDD, and achieves about $R=239/255$12 dB gain over iBDD at BER $R=239/255$13; the reported complexity is less than $R=239/255$14 of a full soft-decision turbo-product decoder in gate count and less than $R=239/255$15 in internal message flow (Rapp et al., 2024).

5. Structural generalizations of staircase decoding

The classical staircase construction can be generalized by increasing the number of component codewords protecting each bit. In generalized staircase codes with arbitrary bit degree $R=239/255$16, the construction is specified by $R=239/255$17 permutations $R=239/255$18, a Golomb ruler $R=239/255$19, and a systematic $R=239/255$20-error-correcting component code of length $R=239/255$21. The parity-check constraint is imposed on the concatenated row

$R=239/255$22

Because the Golomb-ruler and net properties ensure that any two component codewords intersect in at most one bit, the guaranteed minimum weight of an error pattern that can evade all $R=239/255$23 decoders is $R=239/255$24. The generalized iterative decoder still operates in a sliding window and still applies bounded-distance decoding to each component syndrome, but its complexity scales as $R=239/255$25. Simulations with $R=239/255$26 and $R=239/255$27, $R=239/255$28 Hamming components, and various $R=239/255$29 show error floors below $R=239/255$30; one example with $R=239/255$31, $R=239/255$32, $R=239/255$33, $R=239/255$34, and $R=239/255$35 iterations reports a $R=239/255$36 dB gap to the hard-decision Shannon limit at BER below $R=239/255$37 (Shehadeh et al., 2023).

Sub-block rearranged staircase codes modify the block geometry instead of the bit degree. Each code block is obtained by encoding rearranged preceding code blocks and a new information block, where the rearrangement involves sub-block decomposition and transposition. The construction can produce block sizes equal to $R=239/255$38 of those of conventional staircase codes while keeping the same rate and component codes, which makes it possible to use stronger algebraic component codes at similar block size. Decoding remains iterative bounded-distance decoding in a sliding window, but each received block must first be “un-permuted” into the format expected by the component-word decoders. Density evolution and stall-pattern analysis show that the proposed codes can outperform conventional staircase codes in both waterfall and error-floor regions, and the performance can be further improved by using a large coupling width (Qiu et al., 2022).

6. Soft-in/soft-out component decoders and implementation trade-offs

Staircase decoding has also been combined with polar component codes. In the systematic polar-staircase construction, each global iteration sweeps through a sequence of stairs, decodes each systematic polar block by a SCAN decoder, and injects overlap extrinsic LLRs into adjacent stairs. Density evolution is used to order bit-channels, and an additional burst-recovery procedure replaces corrupted overlap LLRs by their twins from neighboring stairs before SCAN decoding. For rate $R=239/255$39, $R=239/255$40, $R=239/255$41, $R=239/255$42, and $R=239/255$43, the polar-staircase scheme reaches BLER $R=239/255$44 at about $R=239/255$45 dB on AWGN, about $R=239/255$46 dB better than the LDPC-stair reference, and the reported end-to-end latency is about $R=239/255$47 cycles versus about $R=239/255$48 cycles for the LDPC comparison (Feng et al., 2018).

A later non-systematic polar staircase framework adds CRC outer codes, polar-aware interleavers, and soft-in/soft-out polar decoders such as Soft-SCL, SCAN, and SCANL. The receiver stores channel reliabilities $R=239/255$49 and extrinsic LLRs $R=239/255$50 for a window of $R=239/255$51 blocks, forms APP inputs by combining them, and can skip future decodings once the CRC on a half-codeword passes. In simulations with $R=239/255$52, $R=239/255$53, and $R=239/255$54, this CRC-aided reduction cuts the number of decodings by about $R=239/255$55–$R=239/255$56 at a BER penalty of only $R=239/255$57–$R=239/255$58 dB at $R=239/255$59. Relative to prior systematic polar staircase work, BER improvements of up to $R=239/255$60 dB are reported, or alternatively considerable complexity reduction at the same BER (Condo et al., 2021).

A different soft staircase direction keeps the blockwise sliding-window architecture but replaces BDD by Chase-II list decoding with a fixed, iteration-independent weighting coefficient $R=239/255$61. In this decoder, all constituent decodes use the same $R=239/255$62, all computations remain in the log domain, and the extrinsic update is $R=239/255$63. For a staircase code of rate about $R=239/255$64 with window size $R=239/255$65, the proposed decoder requires about $R=239/255$66 dB at BER $R=239/255$67, compared with about $R=239/255$68 dB for a Chase-Pyndiah-like sliding-window reference, a gain of $R=239/255$69 dB. Because $R=239/255$70, it can be implemented as a simple right-shift rather than a family of iteration-dependent coefficients (Straßhofer, 13 May 2026).

This suggests that staircase decoding now spans a broad implementation spectrum: pure syndrome-domain BDD, hard-decision miscorrection suppression, marked-bit and ternary hybrid decoders, and soft-in/soft-out or list-based windowed decoders. Across that spectrum, the central structural idea remains unchanged: overlapping component-code constraints are processed locally within a sliding window, and decoder design is driven by the trade-off between miscorrection control, error-floor suppression, soft-information usage, and hardware data flow.