SplitK Partial Fusion in Quantized GEMM

• The technique fuses on-the-fly dequantization with GEMM into a single kernel, significantly improving compute resource utilization and memory bandwidth for quantized inference.
• SplitK partial fusion decomposes the K-dimension into multiple segments, enabling efficient processing of 'skinny' matrices typical in large foundation models like LLaMA.
• Benchmark results on NVIDIA A100 and H100 GPUs demonstrate speedups up to 295% compared to conventional tiling, though challenges include atomic contention and sensitive parameter tuning.

SplitK partial fusion is a technique for accelerating matrix multiplication involving quantized weights, specifically targeting W4A16 quantized inference workloads. It fuses on-the-fly dequantization and general matrix multiplication (GEMM) into a single kernel using a SplitK work decomposition within the Triton programming model. This approach is particularly effective for "skinny" matrix multiplications, such as those found in large foundation models (e.g., LLaMA), where the activation matrix is thin ($m \ll n = k$). SplitK partial fusion improves compute resource utilization and memory bandwidth, delivering speedups of up to 295% compared to conventional data-parallel GEMM tiling, with average boosts of 65% on NVIDIA A100 GPUs and 124% on H100 GPUs (Hoque et al., 2024).

1. Core Algorithm: SplitK Partial Fusion

SplitK partial fusion modifies the standard matrix multiplication workflow for $C \leftarrow AB$ with:

• $A$ as an FP16 matrix of shape $(M \times K)$,
• $B$ as a W4A16-quantized matrix (eight 4-bit weights packed into each int32), of shape $(K \times N)$,
• Per-column scale ($s_n$) and zero-point ($z_n$) parameters for $B$.

Instead of conventional 2D tiling over $(M, N)$, SplitK launches a 3D grid spanning $C \leftarrow AB$0, where $C \leftarrow AB$1 is the number of splits along the $C \leftarrow AB$2-axis (the "split_k" parameter). Each thread block $C \leftarrow AB$3 computes a partial sum over a disjoint segment of $C \leftarrow AB$4, accumulating into a tile $C \leftarrow AB$5 and performing an atomic add to the output matrix $C \leftarrow AB$6.

The fused kernel executes the following for each tile:

1. Parameters: block sizes $C \leftarrow AB$7 and $C \leftarrow AB$8.
2. Launches a grid: $C \leftarrow AB$9, $A$0.
3. Each kernel instance determines its tile position $A$1 and range in $A$2 using

$A$3

where $A$4 is the number of iterations.

1. For each $A$5:
   • Loads an $A$6 tile (FP16) and a packed, quantized $A$7 tile (int32).
   • Dequantizes $A$8 in-register using the provided scales and zero-points.
   • Performs a fused matrix multiply-accumulate.
2. After summing over its $A$9-segment, atomically adds the local accumulator into $(M \times K)$0.

Sample pseudocode:

$s_n$6

2. Mathematical Formulation: Dequantization and SplitK Slicing

Dequantization from 4-bit weights to FP16 is performed per element via:

$(M \times K)$1

where:

• $(M \times K)$2 is the quantized weight,
• $(M \times K)$3 is the scale for output column $(M \times K)$4,
• $(M \times K)$5 is the zero-point for column $(M \times K)$6.

For each 32-bit packed word $(M \times K)$7 holding 8 lanes: \begin{align} w^{(j)}_q &= (P_i \gg 4j) \land 0xF \ w^{(j)}_{\mathrm{fp}} &= s_{n_{\mathrm{start}} + 8i + j} \cdot (w^{(j)}_q - z_{n_{\mathrm{start}} + 8i + j}) \end{align}

SplitK slicing along $(M \times K)$8-dimension: \begin{align} S &= \text{split}k \ P &= \lceil K / (B_k \cdot S) \rceil \ k{\mathrm{off}}(p,\mathit{pid}_k) &= (p \cdot S + \mathit{pid}_k) \cdot B_k \end{align} Each block computes

$(M \times K)$9

Prior to the final atomic reduction into the output matrix $B$0.

3. Triton Kernel Micro-Architecture

The kernel micro-architecture employs:

• Grid dimensions:
  • $B$1 (over $B$2 tiles)
  • $B$3 (over $B$4-axis splits)
• Thread blocks:

Each block typically maps to one CUDA thread array (CTA), commonly using 4 warps (128 threads).

• Thread layout:

Threads each handle one or more elements of the $B$5 accumulator. Tiling values such as $B$6, $B$7 are typical; warps are subdivided to load 16×16 subtiles from $B$8 or $B$9.

• Data movement:
  • $(K \times N)$0 tiles loaded from FP16 global into registers.
  • $(K \times N)$1 tiles loaded as int32, dequantized in registers using per-column scales/zero-points.
  • Matrix multiplications and accumulations are performed in registers (using Tensor Core-compatible instructions).
  • No shared memory buffering is used; tile sizes are tuned for register-level reuse.
  • The accumulator remains in FP32 registers until atomic addition into $(K \times N)$2.
• Control flow:

The main tile/segment loop iterates over $(K \times N)$3 $(K \times N)$4-slices, loading tiles, dequantizing $(K \times N)$5, computing dot-products, and upon completion, atomically merging the block result into the output.

4. Benchmark Results and Performance Profile

Performance has been systematically benchmarked for $(K \times N)$6, $(K \times N)$7 on NVIDIA A100 (PCIe/SXM) and Hopper H100 GPUs (PCIe).

Key results, comparing SplitK to classic data-parallel (DP) tiling:

Platform (split_k)	M=1: SplitK vs DP TFLOPS (Δ)	M=16: SplitK vs DP TFLOPS (Δ)	Peak speedup
A100 80GB (split_k=4)	0.15 vs 0.09 (65%)	4.5 vs 3.5 (28%)	Up to 295% (small dims)
H100 (split_k=8)	2.46 vs 1.10 (124%)	4.1 vs 1.8 (128%)	Up to 295% (N=1024)

Further breakdown:

• For M=1, N=2048 on H100: SplitK delivers 1.85 TFLOPS vs DP's 0.62 TFLOPS (195% increase).
• Nsight Compute (A100, M=16, N=K=4096):
  • Kernel latency: 27.9 μs vs 52.9 μs (48% lower).
  • Achieved DRAM BW: 313 GB/s vs 161 GB/s.
  • Occupancy: 27.8 vs 7.6 warps per SM.
  • SM utilization: 43% vs 21%.

Superior gains are observed for the "llama-style" regime ($(K \times N)$8) due to:

• Low $(K \times N)$9 causing memory-bound conditions for DP.
• SplitK boosting kernel occupancy by multiplying the number of CTAs in flight, hiding memory latency.
• On large-SM H100 architectures, raising split_k to 8 rebalances the load distribution and reduces the "wave" quantization losses of data-parallel tiling.

5. Limitations and Trade-Offs

SplitK partial fusion presents several operational limitations:

• Atomic addition contention: Increasing split_k raises the number of CTAs writing to the same $s_n$0-tile, potentially incurring significant atomic update queuing and serialization.
• Parameter tuning sensitivity: Optimal split_k is architecture-specific (e.g., A100: 4; H100: 8). Larger values can degrade performance due to contention.
• Resource constraints: Increasing $s_n$1, $s_n$2, or $s_n$3 to exploit more parallelism also drives up register pressure and restricts hardware occupancy.
• Supported quantization: The implementation targets W4A16 (4-bit weights to FP16) only. Adapting to other quantization levels (W2, W8) requires a reimplementation of the unpack and dequantization logic.

6. Future Extensions

Potential extensions for SplitK partial fusion include:

• StreamK decomposition: Incorporating techniques such as K-streaming and double-buffered pipelines to further improve $s_n$4-axis parallelism and hide memory latencies.
• Generalized dequantization: Supporting per-group or per-channel quantization, requiring multiple scale/zero arrays and adaptable unpacking logic.
• Autotuning: Employing automated search over $s_n$5 configuration space using Triton, to optimize for specific hardware and workload profiles.

SplitK partial fusion constitutes a hardware-efficient, highly parallel kernel design for W4A16 inference, demonstrating substantial performance gains for memory-bound, skinny GEMM layers found in contemporary foundation model deployments (Hoque et al., 2024).