Software-Based Self-Testing Approach

• Software-Based Self-Testing is a technique that leverages a device’s native programmability to run targeted test routines, ensuring accurate fault activation and observability.
• The approach integrates pure software libraries and hybrid methods that combine hardware support to optimize coverage while reducing test sequence size and execution time.
• SBST frameworks automate test generation and assessment, employing advanced scheduling and fault compaction techniques that yield significant performance improvements for in-field validation.

Software-Based Self-Testing Approach

Software-Based Self-Testing (SBST) comprises a collection of methodologies for verifying correct operation and detecting faults in processor-based or system-on-chip (SoC) devices by executing software test routines directly on the hardware under test. These approaches play a central role in automotive, aerospace, medical, and security-sensitive embedded systems, as they enable in-field, at-speed validation under real operational conditions with minimal hardware overhead. SBST methodology encompasses the generation, execution, and assessment of structured test programs (or self-test libraries), which may be fully software-driven or leverage hybrid software/hardware mechanisms for fault activation, propagation, and observability.

1. Principles and Architectures of SBST

SBST is characterized by leveraging the native programmable resources of a device to perform in-field self-testing, typically by running sequences of carefully designed instructions (test programs, TPs) that stimulate various hardware modules. Each instruction of a TP activates and propagates internal faults to externally observable points, thus mapping software operation onto underlying fault models such as stuck-at or delay defects (Guerrero-Balaguera et al., 2021).

Architecturally, SBST can be realized as:

• Purely software test libraries (STLs) executing as application-like routines.
• Software/hardware hybrid approaches coupling software scheduling and hardware-based pattern generation or response compaction units for enhanced coverage and observability (Mulhem et al., 2024).
• Integrated online and in-field test frameworks utilizing multi-threaded architectures, such as System Hyper Pipelining (SHP), to facilitate non-interfering, periodic self-test within normal SoC operation (Strauch, 2024).

2. Test Program Construction and Compaction

Test program construction generally involves deterministic, ATPG-derived routines targeting combinational logic, pseudorandom-coded sequences for sequential logic, and specialized algorithms for memories and register files. Modern STLs, provided by major semiconductor vendors, are tailored to the underlying microarchitecture and operational constraints (e.g., downtime, memory footprint).

Minimizing the size and execution time of SBST routines without degrading fault coverage is critical for in-field deployment. Formalizing the compaction problem:

• Given an original test sequence $T = \langle i_1, \dots, i_n \rangle$ achieving fault coverage $C(T)$ over fault set $F$, the objective is

$$\min |T_{\mathrm{compact}}| \quad \text{s.t.} \quad C(T_{\mathrm{compact}}) \geq C(T) - \Delta$$

A microarchitectural tracing and single-fault simulation-based compaction algorithm can identify and eliminate non-essential basic blocks with a single simulation run, yielding size reductions up to 93.9% and time reductions up to 95% with a maximum fault coverage degradation $\Delta_C$ < 0.4% (Guerrero-Balaguera et al., 2021).

3. Automation, Workflow, and Framework Instantiations

SBST approaches may be realized by integrating several automation components:

• Test-vector and golden-reference generators, typically driven by random or systematic parameter sweeps with Python or C-based application code (Terzano et al., 10 Apr 2025).
• Configurable CLIs and orchestration tools for full-system integration testing, supporting both simulation and FPGA execution targets.
• In complex SoC or self-organizing algorithms, model-based testing frameworks utilize probabilistic environment profiles (Markov processes) to systematically generate representative scenarios while maintaining state-space tractability (Eberhardinger et al., 2016).

A representative SBST workflow, such as in the TestIt package, consists of:

1. Setup and parameter configuration.
2. Automated test-vector and golden-reference generation.
3. Building and deploying the self-test application.
4. Execution on the target hardware (simulation or FPGA).
5. Output parsing, pass/fail assessment, and metric aggregation (Terzano et al., 10 Apr 2025).

4. Fault Activation, Propagation, and Observability

Proper SBST efficacy requires not only activating latent faults but ensuring their manifestation at observable device interfaces. Fault models include gate-level stuck-at, delay, and bridging faults. Activation coverage is maximized via ATPG-compliant routines; propagation is evaluated via per-instruction tracing and statistical metrics such as propagation probability $P_\mathrm{prop}(i)$.

Observability is fundamentally augmented in hybrid schemes. For example, the use of hardware test pattern generators (TPG) and keyed-hash message authentication code (KMAC) engines achieves both high fault coverage and resistance to signature attacks, with zero observed aliasing for 256-bit digests and compaction rates exceeding 99.6% for long responses (Mulhem et al., 2024).

5. In-Field Integration and Non-Interfering Execution

Cutting-edge SBST architectures integrate self-testing seamlessly with normal system operation:

• Thread-controlled scheduling (SHP) time-slices test routines with application threads, transparently utilizing idle or micro-cycles, ensuring zero interference with real-time operation (Strauch, 2024).
• Redundant thread execution enables ultra-fast single event upset (SEU) detection and recovery within bounded micro-cycle latencies.
• Software-based test scheduling on embedded CPUs enables opportunistic or on-demand health checks, with hybrid approaches allowing both on-chip and remote attestation without exposing internal response data (Mulhem et al., 2024).

6. Evaluation, Metrics, and Experimental Results

SBST effectiveness is commonly evaluated via metrics including:

• Fault coverage $C(T)$ achieved for a given fault set.
• Compaction ratio $R_\mathrm{compact}$ and execution-time reduction $R_\mathrm{time}$.
• Test-cycles-per-net (TCPN) and performance-per-area (PpA) in SoC deployments.
• Area overhead due to test-specific hardware (e.g., KMAC, TPG, thread registers).

Experimental evaluations have demonstrated:

• 100% stuck-at fault coverage on gate-level nets in GIF-based RTL-ATPG flows (Strauch, 2024).
• 11x speedup for system-level test campaigns using automated SBST on FPGA relative to simulation (Terzano et al., 10 Apr 2025).
• KMAC-based signature compaction with hardware overhead <8% LUTs and zero observable aliasing at practical lengths (Mulhem et al., 2024).

Illustrative table summarizing SBST experimental effects (from (Guerrero-Balaguera et al., 2021, Mulhem et al., 2024, Strauch, 2024)):

Metric	Value/Range	Context
Max. TP compaction ratio	93.9%	RISC-V execute unit TPs (Guerrero-Balaguera et al., 2021)
Max. execution-time reduction	95%	SBST programs (Guerrero-Balaguera et al., 2021)
Stuck-at fault coverage (SBST hybrid)	100%	Gate-level nets (Strauch, 2024)
KMAC hardware overhead	<8% LUTs	PULPissimo SoC (Mulhem et al., 2024)
KMAC aliasing rate	$\leq 1/2^{128}$	256-bit digest (Mulhem et al., 2024)
FPGA SBST speedup	11x over simulation	X-HEEP case (Terzano et al., 10 Apr 2025)

7. Limitations, Extensions, and Future Directions

Current SBST methodologies present several boundaries:

• Limited coverage of analog or non-stuck-at fault models without integration of complementary test techniques.
• Complexity of RTL ATPG and interactive coverage refinement as SoC scale increases (Strauch, 2024).
• Restrictions on conditional or heavily branched software constructs in compaction algorithms (Guerrero-Balaguera et al., 2021).
• Requirement for establishing and securing device-specific keys and remote dictionaries in cryptographically protected schemes (Mulhem et al., 2024).

Potential extensions include:

• Generalization to conditional program flows via dynamic analysis.
• Automated partitioning and parallelization for large-scale distributed systems and mixed-signal blocks.
• Dynamic, priority-driven scheduling that adapts to real-time safety requirements.
• Continuous-integration pipelines to provide perpetual, automated in-field self-test and validation for future safety-critical embedded deployments (Guerrero-Balaguera et al., 2021, Strauch, 2024, Mulhem et al., 2024).

SBST continues to evolve as a foundational methodology in the assurance of digital system correctness across domains that demand high reliability, runtime safety, and, increasingly, security against disclosure-oriented adversaries.