Slim NoC: Efficient On-Chip Network Topology

• Slim NoC is an on-chip network topology defined by advanced graph theory that achieves high energy and area efficiency with low-latency communication.
• It leverages degree-diameter graphs and non-prime finite fields to minimize router complexity and support power-of-two node counts for manufacturable VLSI implementations.
• Simulation and DSENT-based evaluations show up to 64% lower latency and significant throughput per power improvements compared to traditional mesh and butterfly networks.

Slim NoC (SN) is an on-chip network (NoC) topology explicitly designed to provide high energy and area efficiency, low-latency communication, and scalable bandwidth for manycore chips comprising hundreds or thousands of processing elements. It leverages advanced graph theory and number theory, particularly degree-diameter graphs and non-prime finite fields, to construct networks that minimize router radix for a given node count and topological diameter, optimizing both physical implementation and communication performance. SN improves upon traditional mesh/torus and modern flattened butterfly networks, as well as off-chip topologies such as Slim Fly and Dragonfly, by addressing key on-chip constraints in area, wiring, and power.

1. Motivations and Theoretical Foundations

The design of Slim NoC originates from the need to balance the trade-off between network diameter and per-router complexity faced by emerging manycore systems. Traditional low-radix NoCs (mesh/torus) scale poorly with node count owing to their large diameter and high hop counts, generating excessive latency. High-radix topologies (flattened butterfly, Clos) reduce path length but demand large routers with numerous ports, inflating power and area due to buffering and crossbar sizing.

Slim NoC seeks a solution near the theoretical optimum for diameter-two networks: the Moore bound, which fixes the maximum possible graph size for given degree and diameter. By generalizing and extending degree-diameter constructions—especially those underlying the Slim Fly topology—Slim NoC enables topologies with minimized router radix (and thus area and energy) for any given node count, especially for powers-of-two which are prevalent in VLSI and chip design.

2. Topological Construction and Finite Field Innovations

Slim NoC introduces two mathematical advances to better align graph-theoretic ideals with VLSI practicality:

Degree-Diameter Graphs: SN applies graph constructions that yield the largest possible network for prescribed diameter and router degree, aiming for diameter two to sharply limit worst-case latency. These constructions are generally based on finite fields and algebraic graph theory, pushing network size toward the Moore bound.

Non-Prime Finite Fields: Unlike Slim Fly, which is limited to topologies constructed over prime or prime-power finite fields, Slim NoC employs hand-constructed addition and multiplication tables to build analogous topologies over non-prime fields (e.g., $q=8,9$), crucial for supporting network sizes (nodes) that are powers of two. This facilitates regular chip floorplans, equal side splits, and more manufacturable VLSI structures without sacrificing the minimized degree-diameter property.

3. NoC-Specific Physical Design and Microarchitectural Extensions

Conventional off-chip-oriented layouts often induce long wires and high buffer demand when adapted to the NoC context. Slim NoC employs specialized methods for placement, buffering, and wire routing:

• Layout Models: SN develops Basic, Group, and Subgroup layout schemes tailored for 2D chip grids and Manhattan wiring. Group/Subgroup layouts, in particular, realize 18–25% reduction in average wire length and overall buffer area compared to naive layouts.
• Buffering Models: Detailed analytical models for both edge-buffers (per-port) and central buffers (CBRs) are used to manage silicon area as core count and network size increase:
  • Edge buffer area: $$\Delta_{eb} = \sum_{i,j} \varepsilon_{ij} \delta_{ij}$$ where $\delta_{ij} = (T_{ij} b |VC|)/L$.
  • Central buffer area: $\Delta_{cb} = N_r (\delta_{cb} + 2k'|VC|)$.
• Router Microarchitecture Augmentation: To further improve energy efficiency and scalability, SN can be augmented with:
  • Central Buffer Routers (CBR): Reduce buffer overhead via shared resources.
  • Elastic Buffers and ElastiStore: Minimize pipeline latches and repeater insertion, reducing both buffer area and wire energy.
  • SMART Links: Enable single-cycle, near-global wire traversal, effectively reducing wire-induced latency.

Two virtual channels and deterministic minimal routing maintain deadlock-freedom, with atomic allocation in CBR configurations.

4. Comparative Evaluation and Performance Metrics

Slim NoC was evaluated via cycle-accurate simulation and DSENT-based physical modeling, using both synthetic (e.g., random, bit-reversal) and real application (PARSEC/SPLASH) traffic patterns. Key findings include:

• Latency: Up to 64% lower than mesh/torus; ~10–13% lower than parameter-matched (flattened) butterfly variants under adverse traffics.
• Throughput per Power: At $N=1296$, SN provides 155–235% improvement over mesh/centralized memory (CM), and 38–54% greater throughput per unit power than partially flattened or fully flattened butterfly topologies.
• Area: SN reduces total NoC area by up to 33% compared to flattened butterfly at large scales.
• Energy-Delay Product (EDP): Delivers at least a 55% reduction versus the best contemporary high-radix topologies.
• Wire and Buffer Scalability: Asymptotic modeling yields $M = \Theta(N^{1/3})$ for average wire length and $\Delta = \Theta(N^{4/3})$ for total buffer area, ensuring manageable physical scaling.

Throughput per Power Improvements (from Table 4)

Topology	N=200 Improvement	N=1296 Improvement
Mesh	+96%	+155%
CM	+97%	+235%
PFBF	+17%	+38%
FBF	+6–12%	+52–54%

Higher values indicate that Slim NoC delivers more flits/cycle/power versus the comparison topology.

5. Physical Realization and Layout Considerations

Slim NoC topologies are realized physically via explicit mapping from logical router groups and subgroups to 2D chip coordinates. Manhattan routing and the selection of Group or Subgroup layouts minimize wire lengths, with the routing tables and group assignments generated according to the non-prime field constructions. The definition for average wire length is:

$$M = \frac{\sum_{i,j} \varepsilon_{ij} (|x_i - x_j| + |y_i - y_j|)}{\sum_{i,j} \varepsilon_{ij}}$$

with $\varepsilon_{ij}=1$ if routers $i,j$ are directly connected.

Attention to wire density, buffer sizing, and physical placement ensures that the scalability benefits of the mathematical topology are not lost in VLSI implementation. When augmented with CBRs or elastic links, these designs further reduce both energy and area overhead from buffer management and long-distance wiring.

6. Summary and Significance

Slim NoC constitutes a significant advancement for scalable on-chip communication networks by providing a topology that is near-optimal with respect to the trade-off between network diameter, router radix, and node count. Through its use of degree-diameter graph theory generalized to non-prime finite fields, Slim NoC supports manufacturable, power-of-two network sizes with minimal router complexity. Comprehensive physical and simulation-based benchmarking establishes Slim NoC’s advantage over both legacy and modern high-radix NoC architectures in area, energy, and performance metrics. SN's layout strategies and router microarchitectural extensions facilitate practical adoption, making it a promising candidate for next-generation manycore systems.