Shift Flow: FPGA Event-based Motion Estimator

• Shift Flow is an event-based motion estimator that discretizes asynchronous events into fixed-duration time bins and produces sparse, quantized velocity estimates.
• It employs a shift-register pipeline to evaluate multiple velocity hypotheses using fixed-width integer operations, ensuring low-latency and deterministic processing.
• The design is optimized for hardware-constrained systems like FPGAs, achieving high directional accuracy and efficient resource use for reactive motion tasks.

Shift Flow, in the sense introduced as EventShiftFlow, is a streaming event-based flow-estimation method designed for hardware-efficient implementation on FPGA platforms. It discretizes asynchronous events into fixed-duration time bins, constructs a 1-bit spatial occupancy history, evaluates multiple velocity hypotheses in parallel, and selects a winner using only fixed-width integer logic, specifically shift registers, counters, comparators, and small LUT-mapped multiplies, with no dividers and no DSP blocks. The method deliberately targets sparse, quantized velocity estimation at each active pixel rather than dense sub-pixel optical flow, and is therefore oriented toward low-latency perception on size-, weight-, and power-constrained systems such as reactive robotic platforms (Bizzi et al., 27 May 2026).

1. Definition and problem setting

Shift Flow is an event-camera motion estimator built around a shift-based datapath. Its central premise is that the core operations of event-based flow estimation—time discretization, spatio-temporal history construction, hypothesis evaluation, and winner selection—can be realized without frame reconstruction, floating-point arithmetic, or iterative optimization. In the formulation described for EventShiftFlow, asynchronous events $(t_k,x_k,y_k,p_k)$ are first binned in time, then thresholded into a binary occupancy representation, after which candidate velocities are scored by tracing diagonals through a shift-register history and counting binary matches (Bizzi et al., 27 May 2026).

This architecture places Shift Flow in a distinct design regime within event-based vision. Rather than estimating dense optical flow fields, it produces a sparse, quantized velocity estimate at each active pixel. This suggests a methodological emphasis on deterministic latency and implementation regularity rather than on continuous-valued per-pixel precision. A plausible implication is that the method is best understood as a hardware-oriented normal-flow cue extractor for downstream control or triggering tasks, rather than as a general-purpose high-fidelity optical-flow replacement.

2. Shift-based computational pipeline

The pipeline is organized into six hardware stages. In Stage A, events are binned by a free-running cycle counter that asserts a bin-complete pulse every $\Delta t/T_{\mathrm{clk}}$ cycles. During each bin, an 8 bit counter per pixel, collapsed along the orthogonal axis, accumulates events; at bin completion, each counter is compared against a threshold $\theta_e$ to produce a 1-bit occupancy vector $E_x(\cdot,i)$. In Stage B, this occupancy is shifted into an $N_x\times L$ register bank, where each row is an $L$-bit shift register and all registers shift left by one on each bin (Bizzi et al., 27 May 2026).

In Stage C, for each active pixel $x_0$ and each discrete jump hypothesis $j\in\{-J,\dots,+J\}$, a candidate trajectory is extracted as a diagonal bit-vector

$$b_j(h)\;=\;G\bigl[x_0 - j\cdot h,\;L - h\bigr],\quad h=1,\dots,L.$$

In Stage D, each hypothesis is scored by a raw popcount,

$R_j \;=\;\sum_{h=1}^L b_j(h),$

implemented as an up-counter per hypothesis lane. To compensate for differing in-bounds trace lengths, the method can either discard hypotheses with too few valid steps or compare normalized scores without division via

$\Delta t/T_{\mathrm{clk}}$0

with multiplication by $\Delta t/T_{\mathrm{clk}}$1 implemented as a left shift when $\Delta t/T_{\mathrm{clk}}$2 is a power of two. Stage E performs winner selection with a comparator tree of depth $\Delta t/T_{\mathrm{clk}}$3, and Stage F outputs the discrete winner $\Delta t/T_{\mathrm{clk}}$4, leaving conversion to physical velocity $\Delta t/T_{\mathrm{clk}}$5 to a host-side lookup or fixed-point divide (Bizzi et al., 27 May 2026).

The resulting datapath is notable because every major operation is expressible in terms of binary storage movement and integer comparison. This suggests that the name “Shift Flow” is not merely descriptive of motion estimation, but also of the implementation principle: the algorithm is literally organized around shifts in time history and shift-based arithmetic.

3. Mathematical formulation

The method begins with a 1-bit occupancy definition derived from time-binned event counts: $\Delta t/T_{\mathrm{clk}}$6 This occupancy drives the update of the spatio-temporal register grid,

$\Delta t/T_{\mathrm{clk}}$7

For each active site and each discrete velocity hypothesis, Shift Flow samples a diagonal trace through this grid: $\Delta t/T_{\mathrm{clk}}$8 The raw score is then

$\Delta t/T_{\mathrm{clk}}$9

When normalized comparisons are required, they are performed without division: $\theta_e$0 where $\theta_e$1 so that $\theta_e$2 (Bizzi et al., 27 May 2026).

These equations encode a discrete motion-consistency test over a binary occupancy history. A plausible interpretation is that Shift Flow estimates motion by identifying the velocity hypothesis whose backtraced occupancy path has maximal temporal support. Because the state is binary and the scoring is popcount-based, the method trades amplitude information and sub-pixel structure for implementation regularity and low arithmetic cost.

4. Streaming control logic and architectural variants

The control structure is expressed as a four-state streaming procedure. In STATE ACCUMULATE_EVENTS, incoming events are buffered while the bin timer remains below $\theta_e$3. On bin completion, STATE THRESHOLD compares each event counter to $\theta_e$4 and clears the counters, followed by STATE SHIFT_GRID, in which each shift register is advanced and the new occupancy bit is inserted. STATE SCORE_PIXELS then evaluates all hypotheses for each active $\theta_e$5, updating score[j], steps[j], and idx[j] across the history depth $\theta_e$6, applying optional normalization tests through cross-product comparisons, and selecting $\theta_e$7 by comparator tree. Finally, STATE OUTPUT emits $$(x_0,j^{<em>,score[j^</em>])`} and returns to accumulation (<a href="/papers/2605.28312" title="" rel="nofollow" data-turbo="false" class="assistant-link" x-data x-tooltip.raw="">Bizzi et al., 27 May 2026</a>).</p> <p>Two implementation styles are described. In the fully pipelined version, all loops over the$$\theta_e$8 hypotheses run in parallel lanes. In a micro-architecture variant, they may instead be executed sequentially. The paper reports both a sequential and a fully parallel latency, making explicit the trade-off between resource use and per-pixel delay. This suggests that Shift Flow is less a single fixed circuit than a design pattern spanning a family of hardware realizations with the same scoring semantics but different parallelization points.

5. FPGA realization and hardware characteristics

The reported implementation targets a Xilinx Artix-7 xc7a100tftg256-2 using Vivado 2025.2 under a 100 MHz constraint. Post-implementation results for the complete UART-to-motion prototype are: 13,326 Slice LUTs, 5,517 Slice Registers, 0 Block RAM tiles, 0 DSP blocks, estimated on-chip power of 0.142 W, and worst setup slack of +0.03 ns at 100 MHz. The scoring latency is 2400 cycles, corresponding to 24 µs at 100 MHz, for the sequential variant, and 21 cycles, corresponding to 210 ns at 100 MHz, for the fully parallel per-pixel variant. Total on-chip storage per axis is under 6 kbit, so both axes fit in under 13 kbit (Bizzi et al., 27 May 2026).

These figures establish the implementation emphasis of Shift Flow. Storage is realized in distributed FFs and shift registers rather than in BRAM, and the absence of DSP blocks is a defining architectural property rather than an incidental optimization. The paper also states that the proposed datapath requires less than 2 kB of storage in the abstract, while the detailed accounting gives under 13 kbit for both axes. Taken together, these statements indicate an intentionally compact design envelope for edge deployment.

6. Empirical performance and operating regime

On synthetic data with 5 % noise, including bars and shapes with velocities in $\theta_e$9 px/µs at 0.005 px/µs step size, Shift Flow attains near-perfect directional accuracy greater than 99 % and magnitude estimates within $E_x(\cdot,i)$0 bin error for single-object motion. In multi-object scenarios, magnitude degrades where traces overlap, described as aperture collisions, but direction remains correct in greater than 90 % of detections. On a real event-camera sequence, specifically the RPG shapes_rotation sequence from DAVIS240C, with parameters $E_x(\cdot,i)$1 ms, $E_x(\cdot,i)$2, $E_x(\cdot,i)$3, $E_x(\cdot,i)$4, $E_x(\cdot,i)$5, and $E_x(\cdot,i)$6, manual-tracking segments with $E_x(\cdot,i)$7 detections yield overall directional accuracy of 99.5 %. Comparison against E2VID→DIS flow shows correct sign transitions at the right times and median bin error $E_x(\cdot,i)$8 (Bizzi et al., 27 May 2026).

The method exhibits a density-dependent operating window. The reported parameter sensitivity analysis identifies best accuracy when occupancy density lies in the 10–40 % range. Below this range, with $E_x(\cdot,i)$9, detections become insufficient; above it, with $N_x\times L$0, correlations become ambiguous. The paper also characterizes the trade-off induced by the choice of $N_x\times L$1: coarser bins improve SNR per bin but coarsen velocity quantization through $N_x\times L$2, whereas finer bins risk producing too little motion across a pixel, causing $N_x\times L$3 and failure of the occupancy threshold. The stated conclusion is that Shift Flow operates at a “sweet-spot” $N_x\times L$4 that yields moderate bin counts and 1 bit occupancy (Bizzi et al., 27 May 2026).

7. Scope, limitations, and relation to adjacent meanings of the term

Shift Flow is explicitly positioned as a sparse, quantized velocity estimator for low-latency tasks such as reactive obstacle avoidance and motion-triggered processing. Its advantages are fixed, deterministic per-bin latency, low resource footprint, low dynamic power, and streaming operation matched to the asynchronous nature of event cameras. At the same time, the method deliberately trades dense sub-pixel optical flow for reduced hardware complexity. The reported failure mode most emphasized in evaluation is degraded magnitude estimation when motions of different velocities intersect, while direction estimation remains substantially more robust (Bizzi et al., 27 May 2026).

The phrase “shift flow” can appear in other technical literatures with unrelated meanings, including symbolic dynamics, phase-shift metrology, and nanofluidic transport. In the present context, however, the term denotes the EventShiftFlow estimator: a hardware-oriented event-based motion-estimation architecture whose defining operations are time binning, binary occupancy history, diagonal hypothesis tracing, popcount scoring, and comparator-based winner selection. This suggests that its significance lies not only in a specific accuracy profile, but in demonstrating that useful event-based flow estimation can be formulated as a fully streaming, divider-free, DSP-free computation.