Optimizing Superconducting Transmon Qubit Shapes

• The paper demonstrates that shape optimization significantly reduces surface dielectric losses, enhancing TLS quality factors by approximately 21.6%.
• Parameterization using B-spline curves and the DIRECT algorithm enables precise control of capacitor pad and junction wire geometries to balance coherence and anharmonicity.
• Simulation and experimental results confirm that optimized wire tapering and pad smoothing improve relaxation time (T1) and scalability without compromising device performance.

Shape optimization of superconducting transmon qubits encompasses the systematic engineering of device geometries, layouts, and circuit elements to maximize coherence, scalability, and quantum control fidelity. Central to this effort is the minimization of dielectric loss—predominantly at surface interfaces—without compromising essential qubit parameters such as anharmonicity, footprint, and gate speed. Recent advances address the challenges of compactness, noise resilience, fabrication variability, and integration with complex quantum architectures, employing both simulation-driven and analytical optimization methodologies.

1. Surface Dielectric Loss as a Design Constraint

Surface dielectric loss, primarily from two-level system (TLS) defects at metal-substrate (MS), metal-air (MA), and substrate-air (SA) interfaces, constitutes a principal decoherence mechanism in superconducting transmon qubits (Eun et al., 2022, Martinis, 2021, Murthy et al., 18 Mar 2025). The surface participation ratio, defined as the fraction of electric energy localized in lossy regions,

$$p_i = \frac{t_i \varepsilon_i / 2}{W} \int_i dS\, |E_i|^2,$$

where $t_i$ and $\varepsilon_i$ are the thickness and permittivity of interface $i$, quantifies the relative loss. The TLS-limited quality factor is thus

$Q_{\mathrm{TLS}}^{-1} = \sum_i p_i \tan\delta_i,$

with $\tan\delta_i$ as the loss tangent of interface $i$. Optimal device performance requires minimizing $p_i$ for relevant interfaces, especially at high electric field concentration regions such as capacitor pad edges and junction wires.

2. Parametric and Global Shape Optimization Techniques

Recent research has introduced parameterization schemes enabling systematic exploration of transmon geometry. The capacitor pad and junction wire are defined with B-spline curves whose control points serve as optimization variables. Numerical optimization—specifically the DIRECT algorithm—targets minimization of MS participation while constraining overall footprint and anharmonicity ($E_C$) (Eun et al., 2022). Full 3D finite-element EM simulations (e.g., Ansys HFSS) are employed for accurate field energy calculation, with adaptive meshing and analytical corrections to address edge singularities. Edge and corner effects—addressed via scaling factors ($c_m$, $c_s$) in analytical formulas—reveal that the junction wiring is a significant and previously underappreciated channel for surface dielectric loss (Martinis, 2021).

3. Wire Geometry, Pad Smoothing, and Trade-offs

Analytical and simulation data show that standard straight wires connecting the Josephson junction to the capacitor pads yield unexpectedly high $p_\mathrm{MS}$. For a straight wire ($d$ length, $r$ width) (Martinis, 2021),

$$p_\mathrm{MS}^\mathrm{sw} \sim \frac{d}{r} \frac{\ln(4r/t) + c_m}{\ln^2(d/r)},$$

with $t$ metal thickness. Introducing a linear or, ideally, continuously varying taper along the wire suppresses participation: $$p_\mathrm{MS}^\mathrm{tw} \sim \frac{\ln(d/r_0)}{S} \cdot \frac{\ln(4Sd/t) + c_m}{\ln^2(4/S)},$$ where $S$ is the taper slope. Optimized splined wires (Eun et al., 2022) and tapers (Martinis, 2021) can reduce wire $p_\mathrm{MS}$ by 25% compared to straight wires, with qualitative suppression extending to reductions in TLS-induced spectral splitting. Spline-based pad parameterization and smoothing transformation efficiently decrease field concentration at geometric discontinuities, further lowering surface participation.

4. Quantitative Impact of Shape Optimization

Comparisons between optimized and reference designs reveal that:

• The optimized capacitor pad reduces MS participation by ~16% and the optimized junction wire by ~26%, with overall improvement in TLS-limited $Q$ and $T_1$ by 21.6% (Eun et al., 2022).
• Quality factors of $Q_{\mathrm{TLS}} = 2.72 \times 10^6$ and $T_1 = 86.5\,\mu$s at 5 GHz are achieved for footprints of $763\,\mu\mathrm{m} \times 751\,\mu\mathrm{m}$, without sacrificing anharmonicity.
• Pad smoothing and wire tapering allow designers to scale up the pad area for reduced pad participation ($\propto$ $1/\sqrt{\text{area}}$) without incurring wire-dominated loss, provided tapering is appropriately engineered.
• The efficacy of these geometric optimizations is validated against both finite-element simulations and experimental $T_1$ data (Eun et al., 2022, Martinis, 2021).

Metric	Standard Pad & Wire	Optimized Pad & Wire	Improvement
Total MS $p_{\textrm{MS}}$ (ppm)	120.3	98.3	−18%
Quality Factor $Q$	$2.24 \times 10^6$	$2.72 \times 10^6$	+21.6%
Relaxation Time $T_1$ ($\mu$s)	71.1	86.5	+21.6%

5. Fabrication and Material Considerations

Shape optimization operates synergistically with process-level improvements, including deep substrate trenching ($>70$ nm for Q saturation), vertical and uniform sidewalls (to avoid increased surface EPR from sloped profiles), and surface encapsulation to prevent formation of lossy oxides (Murthy et al., 18 Mar 2025). The hybrid 3D–2D EPR simulation approach (combining coarse 3D modeling with fine 2D field analysis at interface regions) provides accurate estimates of $p_i$ and $Q_{\mathrm{TLS}}$ when detailed atomistic control is lacking (Moretti et al., 9 Sep 2024). Design methodologies intrinsically consider fabrication tolerances and robustness by ensuring that small geometric perturbations do not cause significant $Q$ degradation.

6. Extensions to Advanced Qubit Paradigms and Device Architectures

Shape optimization frameworks are extendable to a range of device archetypes:

• Compact vacuum-gap capacitors for minimum-footprint, high-density integration and near-unity vacuum participation, crucial for scaling without sacrificing $T_1$ (Zemlicka et al., 2022).
• Inductively shunted (kinemon) and merged-element (mergemon) transmons, where optimizing the inductor loop, shunt geometry, and junction area allows tuning of both anharmonicity and robustness to charge/fabrication noise (Kalacheva et al., 2023, Zhao et al., 2020).
• Large-scale multi-qubit layouts, where geometric scaling, chip routing, and systematic pad/wire optimization maximize uniformity and minimize cross-talk, as demonstrated in 4- and 8-qubit arrays (Gayatri et al., 7 Aug 2025).
• Multi-mode cavity integration, leveraging field distribution engineering to achieve uniform and tunable coupling across multiple modes for Hilbert space expansion (Reineri et al., 2023).
• Placement and sizing of quasiparticle traps for stabilization and fluctuation suppression, strongly dependent on device geometry and wire/pad layout (Hosseinkhani et al., 2017).

7. Conclusion and Prospects

Shape optimization of superconducting transmon qubits—implemented through parametric geometry control, advanced simulation, and global optimization algorithms—has enabled significant reductions in surface participation, extension of coherence times, and increased integration density without compromising quantum control. Further progress is contingent upon advances in hybrid material-geometry co-design (e.g., combining low-loss materials with optimized pad/wire layouts), rapid proxy characterization (e.g., THz near-field and magneto-optical imaging), and the extension of these principles to complex, scalable quantum architectures. These optimizations constitute an essential enabling technology for next-generation fault-tolerant, large-scale superconducting quantum processors.