Reuse Feature SRAM Techniques

• Reuse Feature SRAM is an architectural strategy that increases operations per SRAM access by retaining feature data for multiple reuse events.
• It employs hierarchical SRAM organization and sophisticated scheduling methods, reducing off-chip traffic and improving energy efficiency.
• Key techniques include shared index data reuse, stationarity scheduling, and in-array compute, achieving up to 4000x reuse in diverse applications.

"Reuse Feature SRAM" (Editor's term) denotes a class of architectural techniques that increase the number of useful operations obtained per on-chip SRAM access by keeping feature data, activation windows, tuples, or precomputed intermediates resident in SRAM and near-memory registers long enough to be consumed multiple times before refetch. In the recent literature, this notion appears in several forms: sparse deep-learning accelerators that regularize irregular accesses through shared windows and broadcast registers (Hsu et al., 25 Mar 2025), CNN accelerators that combine full output stationarity with semi input stationarity (Khadem et al., 2021), neural-rendering coprocessors that reuse feature SRAM across rays, ray-packets, and samples (Yuan et al., 9 Oct 2025), and SRAM-processing systems that repurpose cache or SRAM arrays themselves for high-reuse compute in Ising optimization, modular multiplication, and analog in-cache MACs (Raman et al., 13 May 2026, Ku et al., 2024, Chakraborty et al., 15 Sep 2025).

1. Quantitative meanings of reuse

A central feature of reuse-aware SRAM design is that reuse is defined operationally rather than rhetorically. In SACHI, the reuse factor is defined as

$$R=\frac{\text{\# of arithmetic (dot-product) operations}}{\text{\# of SRAM row (or bit-cell) accesses}},$$

with the naïve spin-stationary mode SACHI(n1) giving $R_{\rm n1}=1$, while the mixed-stationary mode SACHI(n3) gives $R_{\rm n3}=N\times R$. When $N\approx 100$ and $R=8$, $R_{\rm n3}\approx 800$, and in fully-connected graphs this can reach $4000\times$ reuse (Raman et al., 13 May 2026).

In the sparse deep-learning accelerator, reuse is expressed through shared-load fan-out. Shared Index Data Reuse defines

$$RF_I(m,s)=|\{n:\mathrm{EffI}_{m,n}=s\}|,\qquad RF_W(n,s)=|\{m:\mathrm{EffW}_{m,n}=s\}|,$$

so that, in the ideal case, each shared load is consumed by up to 16 PEs in the same row or column. The same work also uses

$$\mathrm{MAPM}=\frac{\text{bytes read}+\text{bytes written}}{\text{MAC}},$$

reporting $2.09$ byte/MAC for SparTen and $R_{\rm n1}=1$0 byte/MAC for the proposed design, which corresponds to $R_{\rm n1}=1$1 fewer SRAM accesses (Hsu et al., 25 Mar 2025).

In the neural-rendering coprocessor, reuse is decomposed into three nested phases. The ray-level reuse factor is

$R_{\rm n1}=1$2

with stage 1 reducing EMAs by $R_{\rm n1}=1$3. The RP-level reuse factor is

$R_{\rm n1}=1$4

and the sample-level reuse factor is approximately the feature-SRAM hit rate, $R_{\rm n1}=1$5. Their product gives $R_{\rm n1}=1$6, meaning $R_{\rm n1}=1$7 of what would have been off-chip traffic is now served entirely on-chip (Yuan et al., 9 Oct 2025).

CoDR formulates reuse through access-count reduction: $R_{\rm n1}=1$8 where the naïve schedule repeatedly rereads input patches and partial outputs, while CoDR reduces input accesses to

$R_{\rm n1}=1$9

and reduces output-feature traffic to a single writeback,

$R_{\rm n3}=N\times R$0

This formalization ties reuse directly to SRAM-reference count rather than only to algorithmic sparsity (Khadem et al., 2021).

2. SRAM hierarchies used to expose reusable feature data

The most direct realization of reusable feature SRAM appears in hierarchical organizations that stage sparse or spatially local data from larger SRAM buffers into very small broadcastable storage. The sparse DLA employs a two-level on-chip hierarchy: global SRAM buffers $R_{\rm n3}=N\times R$1 and $R_{\rm n3}=N\times R$2 hold sparse feature activations and sparse weights as compressed streams plus small bitmaps, while shared registers $R_{\rm n3}=N\times R$3 and $R_{\rm n3}=N\times R$4, each with depth $R_{\rm n3}=N\times R$5, broadcast a sliding window of data to $R_{\rm n3}=N\times R$6 PEs. In each cycle, one shared input index and one shared weight index are selected, the corresponding bundles $R_{\rm n3}=N\times R$7 and $R_{\rm n3}=N\times R$8 are moved into registers, and the same bundle is then reused by multiple PEs (Hsu et al., 25 Mar 2025).

CoDR organizes feature storage as three SRAM banks and small register-files inside each PU. Input SRAM is $R_{\rm n3}=N\times R$9 kB and Output SRAM is $N\approx 100$0 kB; each PU’s Input RF stores a tile of

$N\approx 100$1

features, and each PU’s Output RF stores

$N\approx 100$2

accumulators. Banking provides one bank per PU so that all 8 PUs can access input and output feature data without conflict. The architectural point is not only capacity, but residency time: input features stay in RF long enough for semi input-stationary reuse, while outputs remain in RF long enough for fully output-stationary accumulation (Khadem et al., 2021).

In EDR-NR, the hierarchy is structured around rendering locality rather than convolutional tiling. The scheduler operates over micro-grid bitmaps, a feature cache with $N\approx 100$3 banks of $N\approx 100$4 kB each, and an MLP weight cache. The design stores only FEATURE data for accessed fine voxels, not whole 512 micro-voxels, together with 4-tier bitmaps and MLP weights. This reduces total on-chip SRAM from approximately $N\approx 100$5 kB to $N\approx 100$6 kB, a $N\approx 100$7 reduction. The storage hierarchy is therefore itself a reuse mechanism: it narrows the set of resident data to the subset most likely to be hit by spatially proximate rays and samples (Yuan et al., 9 Oct 2025).

3. Scheduling, stationarity, and broadcast as reuse mechanisms

Reuse Feature SRAM is enabled less by raw storage capacity than by dataflow rules that align consumers around the same SRAM-resident data. In the sparse DLA, Effective Index Matching first identifies exactly which element pairs will produce a non-zero MAC by computing $N\approx 100$8, then re-sorts bitmap indexes into masked bitmaps whose $N\approx 100$9s correspond to matching positions. Shared Index Data Reuse then chooses $R=8$0 per row and $R=8$1 per column, allowing a shared bundle of up to 8 consecutive non-zeros to be fetched exactly once per cycle and then reused by up to 16 PEs. PEs whose offsets exceed $R=8$2 idle one cycle so that the shared window can catch up. The schedule converts irregular sparse accesses into a broadcast-style flow (Hsu et al., 25 Mar 2025).

CoDR uses loop ordering and stationarity. Its hybrid schedule is fully output-stationary and semi input-stationary: for each output-channel tile, input tiles are loaded into Input RF, spatial tiles are processed, and after all input tiles are complete, the corresponding output tile is written back exactly once. The paper states that each input tile is loaded only $R=8$3 times in total, while each output tile is written back exactly once. This reduces intermediate-feature SRAM traffic without requiring loss of compression on the weight side (Khadem et al., 2021).

EDR-NR expresses the same principle through a four-stage scheduler. Stage 1 performs Z-order clustering so that 4 rectified rays become one Ray-Packet; stage 2 uses the Lag-First Aggregate Unit to advance the lagging ray first; stage 3 groups ray-packets by coarseVoxelID in the RP-ROB; and stage 4 issues samples out-of-order when their features are already hot in SRAM. The same feature/cache banks remain resident and get reused by dozens of RPs, and the average RPs handled per tag switch increases by $R=8$4. The OoO stage yields an $R=8$5 sample throughput uplift by serving hits immediately while misses wait for DRAM completion (Yuan et al., 9 Oct 2025).

SACHI makes the stationarity design space explicit. Its Algorithm 2 is spin-stationary, Algorithm 3 is IC-stationary, and Algorithm 4 is mixed-stationary. In the mixed-stationary mode, the entire row of $R=8$6 bits is loaded at once, yielding all $R=8$7 partial products in one cycle, followed by one $R=8$8-wide shift-and-add tree and annealer. This is a reuse-aware formulation of cache-resident compute: higher reuse is achieved not by larger storage, but by loading data in a form that maximizes fan-out before the next SRAM access (Raman et al., 13 May 2026).

4. Circuit-level embodiments in SRAM and cache arrays

At circuit level, reuse-aware SRAM can mean that the SRAM array is not only the storage medium but also the compute substrate. SACHI repurposes the L1 cache of a CPU using SRAM-based processing-in-memory techniques. Because modern L1 caches already use an 8T cell with separate read/write ports, the design requires no change to the cell array itself and adds only a small amount, approximately $R=8$9 of CPU-core area, of extra peripheral logic. A bit and its complement are stored in two bitcells in the same column; pre-charged read bit-lines and driven read-word-lines implement purely digital XNOR, and the discharged RBL is accumulated in a small array of full-adders at the L1 periphery. No DAC or ADC is needed, and the read port multiplexes between normal and compute mode (Raman et al., 13 May 2026).

ModSRAM provides a different SRAM-PIM realization. It uses a $R_{\rm n3}\approx 800$0 array of 8T SRAM cells with Logic-SA modules that detect three distinct voltage levels and thus enable all 3-input logic functions, including XOR3 and MAJ, in one cycle. A small number of reserved word-lines in each column serve as LUT rows storing radix-4 precomputation of $R_{\rm n3}\approx 800$1 and carry-overflow correction values. Because the same $R_{\rm n3}\approx 800$2 and $R_{\rm n3}\approx 800$3 remain fixed across all iterations, LUT-radix4 and LUT-overflow entries are reused without reload, while only the evolving sum and carry rows change each cycle. This moves reuse from dataflow scheduling into persistent in-array intermediate storage (Ku et al., 2024).

NVM-in-Cache extends SRAM reuse into hybrid analog PIM. It inserts two RRAM devices into a conventional 6T-SRAM cell to form a 6T-2R bit-cell, with no bit-cell area overhead. During computation, VDD lines serve as accumulation paths, and for $R_{\rm n3}\approx 800$4 rows the currents sum as

$R_{\rm n3}\approx 800$5

The column current is integrated on a sample-and-hold capacitor and digitized by a 6-bit SAR-ADC. The two-cycle PIM sequence preserves the SRAM state and restores the original $R_{\rm n3}\approx 800$6 bits after computation. Here reuse is embodied in the fact that existing cache-resident state participates in massively parallel MACs without cache-flush overhead (Chakraborty et al., 15 Sep 2025).

5. Reported outcomes across representative systems

The empirical literature reports reuse in several non-equivalent metrics: SRAM-reference reduction, cache-hit amplification, performance per watt, time-to-solution, and cycle count. The table summarizes the principal reported outcomes.

System	Reuse mechanism	Reported outcome
Sparse DLA (Hsu et al., 25 Mar 2025)	EIM + SIDR with shared windows from BufI/BufW to RegI/RegW	$R_{\rm n3}\approx 800$7 fewer SRAM accesses; $R_{\rm n3}\approx 800$8 TOPS/W; $R_{\rm n3}\approx 800$9 improvement in power efficiency compared to SIGMA
EDR-NR (Yuan et al., 9 Oct 2025)	Reuse across rays, ray-packets, and samples with four-stage scheduler	$4000\times$0 reduction in on-chip SRAM consumption; $4000\times$1 normalized energy efficiency; $4000\times$2 normalized throughput
CoDR (Khadem et al., 2021)	Full output stationarity and semi input stationarity in feature SRAM/RFs	SRAM access reduced by $4000\times$3 and $4000\times$4; total energy reduced by $4000\times$5 and $4000\times$6
SACHI (Raman et al., 13 May 2026)	Reuse-aware cache-resident Ising computation with stationarity modes	reuse factors up to $4000\times$7; up to $4000\times$8 faster and $4000\times$9 energy reduction vs. BRIM
ModSRAM (Ku et al., 2024)	LUT rows and carry-save in-memory reuse for modular multiplication	$$RF_I(m,s)=|\{n:\mathrm{EffI}_{m,n}=s\}|,\qquad RF_W(n,s)=|\{m:\mathrm{EffW}_{m,n}=s\}|,$$0 cycle reduction; $$RF_I(m,s)=|\{n:\mathrm{EffI}_{m,n}=s\}|,\qquad RF_W(n,s)=|\{m:\mathrm{EffW}_{m,n}=s\}|,$$1 cycles for 256 b mul-mod; $$RF_I(m,s)=|\{n:\mathrm{EffI}_{m,n}=s\}|,\qquad RF_W(n,s)=|\{m:\mathrm{EffW}_{m,n}=s\}|,$$2 area overhead
NVM-in-Cache (Chakraborty et al., 15 Sep 2025)	Compute-on-powerline MAC in 6T-2R cache cells	$$RF_I(m,s)=|\{n:\mathrm{EffI}_{m,n}=s\}|,\qquad RF_W(n,s)=|\{m:\mathrm{EffW}_{m,n}=s\}|,$$3 TOPS; $$RF_I(m,s)=|\{n:\mathrm{EffI}_{m,n}=s\}|,\qquad RF_W(n,s)=|\{m:\mathrm{EffW}_{m,n}=s\}|,$$4 TOPS/W; $$RF_I(m,s)=|\{n:\mathrm{EffI}_{m,n}=s\}|,\qquad RF_W(n,s)=|\{m:\mathrm{EffW}_{m,n}=s\}|,$$5 CIFAR-10 accuracy with ResNet-18

These results are not directly interchangeable because the workloads differ: sparse MAC scheduling, CNN inference, neural rendering, Ising optimization, ECC modular multiplication, and analog DNN inference. Even so, the measurements consistently attach performance or energy gains to reduced SRAM or external-memory traffic, increased fan-out per load, or retention of reusable intermediate values in SRAM itself.

6. Design trade-offs, limitations, and recurring misconceptions

The collected literature indicates that reuse is not equivalent to merely increasing SRAM size. EDR-NR explicitly states that larger feature SRAM would further cut miss rate, but adds area and leakage; it also adds that more aggressive OoO queues reduce stalls but complicate control logic, and that AABB pruning costs extra comparators per RP (Yuan et al., 9 Oct 2025). A plausible implication is that reusable feature SRAM is governed by a control-and-locality trade-off as much as by capacity.

A second recurring misconception is that the most aggressive reuse mode is always the best operating point. SACHI reports that the most aggressive reuse mode, n3, must rewrite the entire compute array once it is full, which in highly sparse graphs can slightly degrade CPI; accordingly, SACHI(n2) sometimes out-performs n3 on mid-sized sparse COPs. The same work also notes streaming overhead once COPs exceed on-chip L1/L2 capacity and states that 8-bit $$RF_I(m,s)=|\{n:\mathrm{EffI}_{m,n}=s\}|,\qquad RF_W(n,s)=|\{m:\mathrm{EffW}_{m,n}=s\}|,$$6 is the sweet spot, because below 8 bits the number of SA iterations rises sharply and above 8 bits the extra array footprint is often unnecessary (Raman et al., 13 May 2026).

A third limitation concerns specialization of reusable SRAM state. In ModSRAM, LUT entries are precomputed for one $$RF_I(m,s)=|\{n:\mathrm{EffI}_{m,n}=s\}|,\qquad RF_W(n,s)=|\{m:\mathrm{EffW}_{m,n}=s\}|,$$7 and one $$RF_I(m,s)=|\{n:\mathrm{EffI}_{m,n}=s\}|,\qquad RF_W(n,s)=|\{m:\mathrm{EffW}_{m,n}=s\}|,$$8; general-purpose use requires either reloads or larger multi-LUT capacity. The design also incurs sense-amp complexity and must manage yield and variation sensitivity when more than three word-lines are activated (Ku et al., 2024). NVM-in-Cache identifies a different bottleneck: ADC latency and area, with the ADC occupying approximately $$RF_I(m,s)=|\{n:\mathrm{EffI}_{m,n}=s\}|,\qquad RF_W(n,s)=|\{m:\mathrm{EffW}_{m,n}=s\}|,$$9 of macro area, while RRAM write-voltage and endurance introduce additional device-level trade-offs (Chakraborty et al., 15 Sep 2025).

Taken together, these constraints show that reusable feature SRAM is a co-design problem. The recurring successful pattern is to align SRAM organization, schedule, and compute primitive so that the same resident data can be consumed by many operations before replacement. In CNNs and sparse DLAs, this appears as stationarity and broadcast. In neural rendering, it appears as spatially coherent packet scheduling and bank-balanced feature caches. In SRAM-PIM and cache-reuse systems, it appears as in-array logic, LUT rows, and compute modes that turn SRAM residency into direct computational leverage.