RePart: Topology-Aware Hypergraph Partitioning

• RePart is a multilevel hypergraph partitioning framework for multi-FPGA systems that optimizes inter-FPGA communication by minimizing total hop distance, achieving a 52.3% reduction over state-of-the-art methods.
• It integrates FPGA-aware dynamic coarsening, heat-value guided assignment, and replication-deletion supported refinement to address resource balance and topology constraints.
• Empirical evaluations on Titan23 and EDA Elite benchmarks demonstrate significant improvements, including an 11.1x speedup and substantial runtime reductions compared to conventional partitioners.

Searching arXiv for the exact RePart paper and closely related partitioning context. RePart is a fully customized multilevel hypergraph partitioning framework for multi-FPGA systems (MFS) that integrates logic replication with topology-aware optimization. It is designed for the setting in which a design netlist must be partitioned across FPGAs that connect only to a limited number of neighbors through bandwidth-constrained links, so inter-FPGA communication cost depends on network topology rather than on cut size alone. The method combines FPGA-aware dynamic coarsening, heat-value guided assignment, and replication-deletion supported refinement, and is evaluated on the Titan23 and EDA Elite Challenge Contest benchmarks, where it is reported to reduce total hop distance by 52.3% on average over state-of-the-art hypergraph partitioners with an 11.1x speedup (Fu et al., 1 Apr 2026).

1. Problem setting and design motivation

RePart addresses partitioning for MFS, where the target hardware is a sparse FPGA network rather than a complete interconnect. In this setting, communication between two FPGAs may require multiple hops, and the cost of a cut net depends on where its endpoints are placed in the topology. The paper identifies two limitations of conventional MFS-aware partitioning methods: conventional hypergraph partitioners focus solely on cut size and ignore topological structure, and they leave substantial FPGA resources unused due to conservative balance margins (Fu et al., 1 Apr 2026).

This problem differs materially from classic hypergraph partitioning. Traditional partitioners mainly optimize cut size and often assume homogeneous partitions and uniform interconnect cost. In an MFS, however, topology matters, communication cost is hop-dependent, resource constraints are multi-dimensional, and communication is additionally shaped by I/O pin and hop constraints. RePart therefore formulates partitioning as a topology-aware optimization problem under multiple FPGA resource limits rather than as a pure minimum-cut problem.

A common misconception in this area is that minimizing cut size is sufficient for good MFS deployment. RePart is explicitly built against that premise: a cut edge crossing adjacent FPGAs is cheaper than one crossing distant FPGAs, so a topology-oblivious minimum-cut solution can still be communication-expensive. The framework consequently prioritizes total hop distance as its main objective.

2. Optimization model and objective function

RePart models the design-under-test as a hypergraph $H(V,E)$, where hyperedges represent nets and vertex assignments correspond to FPGA placement. Its main objective is the communication metric termed total hop distance. The paper defines the communication cost of a hyperedge $e$ as

$$\text{hop\_distance}(e)=\sum_{\hat{v}\in N(e)} \text{hop}(\text{part}(\text{source}(e)), \hat{v}),$$

and the overall objective as

$$\text{total\_hop\_distance}=\sum_{e\in E} w_e \cdot \text{hop\_distance}(e).$$

Here, $w_e$ is the weight of net $e$, equal to the number of signals in the net; $\text{source}(e)$ is the source vertex of $e$; $N(e)$ is the set of FPGAs containing drain vertices of $e$; $e$0 is the FPGA assignment of vertex $e$1; and $e$2 is the shortest-path hop distance in the FPGA network $e$3.

The paper argues that this objective directly reflects communication latency, bandwidth contention, TDM ratio, and routing pressure in MFS. This is significant because it replaces the proxy objective of cut size with a network-aware quantity that is aligned with the physical deployment environment.

Resource feasibility is modeled as a multi-resource balance problem. Circuit vertex resource usage is denoted by $e$4 for resource type $e$5, and average FPGA capacity by $e$6. RePart seeks assignments that are feasible under these constraints, and its replication and deletion operations are also required to respect them. This makes the method simultaneously communication-aware and capacity-aware.

3. Multilevel framework

RePart uses a three-stage multilevel pipeline: FPGA-aware dynamic coarsening, heat-value guided assignment, and replication-deletion supported refinement (Fu et al., 1 Apr 2026). Each stage is specialized for MFS rather than adapted from a topology-agnostic partitioner.

In the coarsening stage, RePart merges strongly connected vertices into hypernodes while accounting for resource balance. For node pair $e$7, it defines a connectivity score

$e$8

where $e$9 is the set of hyperedges incident to $$\text{hop\_distance}(e)=\sum_{\hat{v}\in N(e)} \text{hop}(\text{part}(\text{source}(e)), \hat{v}),$$0. To penalize merges that would create resource-heavy coarse clusters, it defines

$$\text{hop\_distance}(e)=\sum_{\hat{v}\in N(e)} \text{hop}(\text{part}(\text{source}(e)), \hat{v}),$$1

and the merge priority

$$\text{hop\_distance}(e)=\sum_{\hat{v}\in N(e)} \text{hop}(\text{part}(\text{source}(e)), \hat{v}),$$2

High $$\text{hop\_distance}(e)=\sum_{\hat{v}\in N(e)} \text{hop}(\text{part}(\text{source}(e)), \hat{v}),$$3 therefore favors pairs that are both strongly connected and reasonably balanced. A key detail is that $$\text{hop\_distance}(e)=\sum_{\hat{v}\in N(e)} \text{hop}(\text{part}(\text{source}(e)), \hat{v}),$$4 is not fixed: the paper describes a logarithmic scaling with coarsening level $$\text{hop\_distance}(e)=\sum_{\hat{v}\in N(e)} \text{hop}(\text{part}(\text{source}(e)), \hat{v}),$$5, and its ablation reports that a dynamic schedule increasing $$\text{hop\_distance}(e)=\sum_{\hat{v}\in N(e)} \text{hop}(\text{part}(\text{source}(e)), \hat{v}),$$6 from 0.5 to 3.5 outperforms fixed $$\text{hop\_distance}(e)=\sum_{\hat{v}\in N(e)} \text{hop}(\text{part}(\text{source}(e)), \hat{v}),$$7, giving about 20% lower average THD than the fixed-$$\text{hop\_distance}(e)=\sum_{\hat{v}\in N(e)} \text{hop}(\text{part}(\text{source}(e)), \hat{v}),$$8 variant.

In the assignment stage, RePart introduces topology-aware heat metrics for both FPGAs and nodes. It defines

$$\text{hop\_distance}(e)=\sum_{\hat{v}\in N(e)} \text{hop}(\text{part}(\text{source}(e)), \hat{v}),$$9

with $$\text{total\_hop\_distance}=\sum_{e\in E} w_e \cdot \text{hop\_distance}(e).$$0, and then

$$\text{total\_hop\_distance}=\sum_{e\in E} w_e \cdot \text{hop\_distance}(e).$$1

More central FPGAs have smaller $$\text{total\_hop\_distance}=\sum_{e\in E} w_e \cdot \text{hop\_distance}(e).$$2 and therefore higher heat. Node importance is measured by

$$\text{total\_hop\_distance}=\sum_{e\in E} w_e \cdot \text{hop\_distance}(e).$$3

Assignment uses depth-first backtracking with pruning when the current partial solution exceeds the best THD found so far, when communication utilization violates constraints, or when FPGA resource capacity is exceeded. A deep backtracking mechanism is triggered when consecutive solutions have normalized cost difference less than 2%, with the stated purpose of escaping local minima. Among the tested assignment variants, assign-nodes performs best and is used in the final system.

4. Logic replication and refinement strategy

The refinement stage extends traditional local improvement with logic replication and deletion (Fu et al., 1 Apr 2026). RePart supports four operations: move, exchange, replicate, and delete. This is one of the framework’s central departures from conventional partitioners.

Replication is used to reduce inter-FPGA communication by placing a local copy of a node on another FPGA. The paper states that this can reduce total hop distance because a drain node can access a local copy of its source rather than communicating across the FPGA network. At the same time, replication consumes FPGA resources and can reduce room for later optimization steps. RePart therefore pairs replication with deletion, which removes unnecessary replicas to reclaim capacity. The paper states that delete is executed when its gain is zero or positive, prioritizing resource recovery even when immediate THD improvement is not required.

This pairing is important because replication is not uniformly beneficial. The paper’s ablation notes that in case 10, the variant with move, exchange, and replication can be worse than move plus exchange alone because replication occupies too much capacity; adding deletion recovers and improves performance. This directly addresses the misconception that more replication always improves placement quality.

To manage local-search state efficiently, RePart maintains gains in a $$\text{total\_hop\_distance}=\sum_{e\in E} w_e \cdot \text{hop\_distance}(e).$$4-Heap data structure: one heap for cross-FPGA exchange opportunities, and $$\text{total\_hop\_distance}=\sum_{e\in E} w_e \cdot \text{hop\_distance}(e).$$5 heaps each for move, replicate, and delete, where $$\text{total\_hop\_distance}=\sum_{e\in E} w_e \cdot \text{hop\_distance}(e).$$6 is the number of FPGAs. After each operation, hop distance, resource usage, communication utilization, and neighboring gains are updated incrementally. The paper reports that this incremental gain-update mechanism yields about 2.27x acceleration over naive full recomputation, with identical solution quality.

5. Empirical evaluation

The reported evaluation uses two benchmark families: Titan23 and EDA Elite Challenge Contest Problem 3 (Fu et al., 1 Apr 2026). Titan23 is paired with two MFS instances from ICCAD’19, SampleInput and synopsys02. The EDA contest benchmark contains 10 test cases, case01 through case10, with weighted hyperedges and more complex resource constraints. The MFS instances vary from 4 to 64 FPGAs, and each EDA case uses 8 resource types: FF, LUT, BUFG, TBUF, DCM, BRAM, DSP, and PP.

The implementation is in C++, compiled with g++ 11.4.0, and evaluated on a machine with an Intel Xeon PLATINUM 8558P 2.7-GHz CPU running Ubuntu 22.04. The main baselines are KaHyPar and the 1st-place and 2nd-place EDA contest winners; for cut-size comparison on Titan23 SampleInput, the paper also compares with TopoPart, Li et al., and RepPart. The evaluation metrics are total hop distance, runtime, and, secondarily, cut size.

The main quantitative findings are summarized below.

Evaluation	RePart result	Comparison
Average THD on benchmarks	52.3% reduction	over state-of-the-art hypergraph partitioners
Overall runtime	11.1x speedup	over state-of-the-art hypergraph partitioners
EDA Contest average ratio	0.47	vs 0.545 for 1st place, 0.91 for 2nd place, 1.00 for KaHyPar
Titan23 / synopsys02 runtime	98.1% reduction	vs KaHyPar
Titan23 SampleInput cut-size ratio	0.019	vs 1 for TopoPart, 0.049 for Li et al., 0.022 for RepPart

The EDA contest results imply a 48.3% reduction versus the 2nd-place solution and a 14.0% reduction versus the 1st-place solution. On Titan23/synopsys02, the paper reports a 52.3% THD reduction versus KaHyPar and a 98.1% runtime reduction. Although RePart is optimized for THD rather than cut size, it also performs strongly on cut size in the Titan23 SampleInput comparison.

The ablations clarify the contribution of each phase. Dynamic coarsening with $$\text{total\_hop\_distance}=\sum_{e\in E} w_e \cdot \text{hop\_distance}(e).$$7 scheduled from 0.5 to 3.5 is better than fixed $$\text{total\_hop\_distance}=\sum_{e\in E} w_e \cdot \text{hop\_distance}(e).$$8. The assign-nodes assignment variant performs best among the tested assignment strategies. In refinement, using all four operations yields a 2.15x reduction in average THD compared to no refinement and a 1.39x reduction compared to move plus exchange only. These results indicate that the gains are distributed across coarsening, assignment, and refinement rather than arising from a single isolated module.

6. Significance, scope, and interpretation

RePart’s central significance is methodological: it reframes MFS partitioning as a joint problem of topology-aware communication minimization and resource-aware logic replication. Rather than treating spare FPGA capacity as a passive balance margin, it uses replication and deletion as active optimization operators. The paper’s reported results suggest that this design choice is effective when the physical interconnect is sparse and hop-dependent.

The framework is also notable for optimizing the entire multilevel pipeline. Coarsening is resource-aware, assignment is topology-aware and search-based, and refinement is replication-aware. This end-to-end specialization distinguishes RePart from approaches that insert only a topology-aware cost into an otherwise conventional partitioner.

Practically, the paper argues that RePart is relevant to rapid prototyping and VLSI emulation flows. By minimizing total hop distance instead of only cut size, it better models real communication cost in sparse FPGA networks; by using logic replication, it makes better use of spare FPGA capacity; and by reducing runtime substantially, it becomes more suitable for iterative design flows.

Its scope, however, is the MFS setting defined by the paper. The reported evidence is tied to Titan23, synopsys02, and the EDA Elite Challenge cases, with performance measured primarily by THD and runtime under those benchmarks. A plausible implication is that the framework will be most advantageous when topology is a first-order constraint and conservative balance margins leave enough headroom for selective replication. Within that scope, RePart is best understood as a topology-aware, replication-enabled partitioner whose main contribution is to align multilevel hypergraph partitioning with the actual communication structure of multi-FPGA hardware.