RapidStream IR: FPGA Synthesis Framework

• RapidStream IR is an extensible high-level physical synthesis infrastructure that models mixed-source FPGA designs with explicit physical and hierarchical constraints.
• It employs device-aware optimizations such as multi-level pipelining and spatial partitioning to boost operating frequencies by 7%–62% while preserving resource efficiency.
• The framework seamlessly integrates HLS outputs, vendor IPs, and handwritten RTL, enabling automated transforms and rapid prototyping of advanced synthesis algorithms.

RapidStream IR is an extensible high-level physical synthesis (HLPS) infrastructure designed to address the performance bottlenecks associated with the growing complexity of large-scale FPGA accelerators. Traditional FPGA HLS flows, such as those provided by Vitis HLS or Intel HLS, generate untimed RTL without direct consideration of the underlying physical layout, resulting in non-optimal operating frequencies due to long, un-pipelined interconnects and localized congestion. RapidStream IR (RIR) introduces a unified, flexible intermediate representation (IR) capable of modeling mixed-source designs—supporting HLS blocks, vendor IPs, and handwritten RTL—while enabling physical-aware optimizations including multi-level hierarchical pipelining, spatial partitioning, and portable integration with evolving target FPGA devices. Experimental results demonstrate 7%–62% operating frequency improvements across a range of designs and platforms, all while maintaining minimal impact on resource utilization and offering extensibility for future research initiatives (Lau et al., 2024).

1. Motivation and Design Challenges

The primary motivation for RapidStream IR arises from limitations in conventional HLS flows, which often overlook the physical realities of modern FPGA architectures. Notable issues include:

• Un-pipelined Cross-Region Interconnects: HLS-generated blocks may be clustered to reduce wirelength without introducing necessary pipelining across die or region boundaries, creating global critical paths that limit achievable clock frequency.
• Local Congestion: Downstream placement tools may amplify congestion by ignoring the latency requirements of signals crossing device boundaries.
• Hierarchy and Source Integration Limitations: Existing tools typically lack mechanisms for hierarchical pipelining, and manual reworking is required to integrate designs across mixed sources and new device platforms.

RapidStream IR addresses these challenges by enabling high-level, device-aware optimizations through explicit representation of logic, interconnect, and spatial constraints within an extensible IR. This framework supports design hierarchy reconstruction, protocol inference, and physical-aware partitioning, making it possible to target heterogeneous, user-customizable, or next-generation FPGAs (Lau et al., 2024).

2. Intermediate Representation Structure

RapidStream IR is formally defined as $\mathrm{IR} = (M, W, I, S)$, where:

• $M = \{m_1, \ldots, m_n\}$ is the set of modules, each $m = (P, U, A, s)$ with
  • $P = \{p_1, \ldots, p_k\}$ (ports: name, direction, width),
  • $U$ (submodules),
  • $A$ (annotations),
  • $s$ (spatial annotation).
• $W = \{w_1,\ldots,w_\ell\}$ is the set of wires, each $w = (\mathrm{src}(w), \mathrm{dst}(w))$, connecting module ports.
• $I = \{f_1,\ldots,f_r\}$ is the set of interfaces, each $f = (F_\mathrm{ports}, \tau)$ where $F_\mathrm{ports}$ is a subset of ports involved in a pipeline protocol and $$\tau \in \{\mathrm{feedforward}, \mathrm{handshake}\}$$.
• $S = \{s_1, \ldots, s_n\}$ contains spatial annotations, $$s_i = (\mathrm{slot\_id}, x_\mathrm{min}, y_\mathrm{min}, x_\mathrm{max}, y_\mathrm{max})$$.

Key constructs enable:

• Hierarchy Reconstruction: Modules are annotated with sub-modules and ports, supporting both flat and hierarchical organization.
• Protocol Capture at Any Hierarchical Level: Interfaces are recursively inferred upward and laterally, supporting the insertion of pipeline registers or FIFOs based on feedforward or handshake semantics.
• Spatial Modeling: Device-specific slots ("virtual devices") are described via spatial annotations to allow physical constraints to drive placement and pipelining.

This representation enables IR transformation passes to operate generically on the design, providing hooks for physical-aware synthesis while preserving original source semantics (Lau et al., 2024).

3. Pass Infrastructure and Physical Optimization Flow

The RapidStream IR framework is architected with three main extensible components:

• Plugins: Modules for importing (e.g., from Vitis/Intel HLS, XCI), analyzing, and exporting to Verilog/VHDL or vendor-specific formats.
• IR Core: Data structures for modules, wires, interfaces, and device modeling.
• Transformation Passes: Pure IR-to-IR transformations supporting scripting in Python, Rust, or other languages.

Major transformation passes include:

• Hierarchy Rebuild: Exposes internal submodule connections by grouping and creating auxiliary modules, facilitating analysis and further partitioning.
• Interface Inference: Deduces interface protocols recursively from submodule structure, assigning parent-child interfaces when port sets match.
• Partition and Passthrough: Utilizes union-find operations on the netlist (excluding clock/reset) to form partitionable components, eliminating trivial splits.
• Flatten and Group: Converts hierarchical designs into a flat graph for partitioning (flatten), restoring hierarchy post-floorplanning (group).
• Auto Floorplan Refinement (ILP): Solves an integer linear program with variables $x_{m,s} \in \{0,1\}$ (assign module $m$ to slot $s$), subject to resource and wirelength constraints, with the objective to minimize estimated total wire delay:

$$\min_{x} \sum_{(m,n)\in E} \sum_{s,t} x_{m,s} x_{n,t} D_\mathrm{wire}(s,t)$$

• Pipeline Stage Insertion: Inserts flip-flop registers (feedforward) or relay-station FIFOs (handshake) based on computed pipeline depth:

$$d_j = \left\lceil \frac{D_\mathrm{wire}(s, t)}{T_\mathrm{clk}} \right\rceil$$

A practical implication is that these modular passes support programmable, composable optimization flows, facilitating both wide automation and easy integration of new research algorithms (Lau et al., 2024).

4. Integration, Portability, and Toolchain Support

RapidStream IR supports robust integration pathways for mixed-source FPGAs and portability to new device classes:

• Source Integration: Importers handle HLS output (Vitis, Intel), vendor IP metadata (e.g., XCI), or in-line pragmas (e.g., // pragma handshake) for leaf module generation.
• Round-Trip Fidelity: Original RTL or IP binaries are embedded verbatim within module metadata, enabling accurate source-preserving transformations.
• Virtual Device Specification: Users define physical resource slots by part number or Vivado Pblock region; device capacity and wire budgets are automatically polled for tools such as Vivado.
• Export Flexibility: Generates standard HDL (Verilog/VHDL), constraint files (Pblocks, UCF), and Xilinx Object bundles, maintaining compatibility across major toolchains and hardware targets.

This architecture enables seamless retargeting to user-customizable or emerging FPGA platforms with negligible manual intervention, addressing a key limitation of prior HLPS proposals (Lau et al., 2024).

5. Extensibility, Scripting, and Research Use Cases

RapidStream IR is designed for extensibility and rapid prototyping of research and production optimization passes:

• Floorplan Exploration: A plugin (207 LoC Python) sweeps resource limits per slot, enabling automated Pareto tradeoff studies between congestion and global wirelength—integrating with the AutoBridge floorplanner.
• Parallel Synthesis: A plugin (299 LoC Python) black-boxes each slot for parallel Vivado HLS/RTL synthesis, then merges netlists with RapidWright. This resulted in a 2.5× synthesis speedup for CNN accelerators scaling from 13×4 to 13×12 systolic arrays.
• Design Debugging and Instrumentation: Users have exploited RIR's pass model to insert performance-counter IPs between handshake interfaces, demonstrating flexible instrumentation capabilities.

These extensibility features facilitate adoption for a broad array of research and commercial applications and support experimentation with novel HLPS and device-aware methodologies (Lau et al., 2024).

6. Experimental Results and Performance Metrics

RapidStream IR demonstrates significant improvements in design frequency across diverse workloads and FPGA platforms with minimal impact on resource utilization. Table 1 summarizes results on convolutional-neural-networks (CNN), LLM accelerators, and genomics pipelines:

Benchmark	Device	Original MHz	RIR MHz	Δ (%)
CNN 13×4	U250	233	335	+44%
CNN 13×8	U250	244	332	+36%
LLM Accelerator	U280	150	243	+62%
LLM Accelerator	VP1552	198	258	+30%
Minimap2	VP1552	263	285	+8%
KNN	U280	292	292	0%

Across six devices, the average frequency gain is +39% (treating unroutable designs as 0 MHz gains), or +50% when disregarding unroutable cases. Post-optimization, memory, LUT, DSP, BRAM, and URAM utilization changes by less than 1%. This suggests that RIR achieves substantial frequency improvements without incurring area penalties (Lau et al., 2024).

7. Future Research Directions

Planned and ongoing research directions for RapidStream IR include:

• Automated NoC Synthesis: Leveraging interface statistics (e.g., $f_j$ bandwidths) to automatically instantiate routers or multicast FIFOs for scalable on-chip network inference.
• Parallel Place & Route: Integration with RapidWright for simultaneous slot-level placement and eventual netlist merging.
• On-Chip Profiling and Dynamic Instrumentation: Extension of the IR to support automatic wrapping of interfaces with event-driven monitors or fuzzing engines, enabling advanced debugging and adaptive optimization.

A plausible implication is that the unification of logical, protocol, and physical annotations in RIR will facilitate efficient implementation of increasingly complex system-on-chip architectures on FPGAs and serve as a foundation for the next generation of HLPS research (Lau et al., 2024).