Racetrack Memory (RTM) Overview

• Racetrack Memory (RTM) is a non-volatile memory technology that uses magnetic domains in nanowires for high-density storage with low latency access.
• It employs current-induced domain wall or skyrmion motion to shift bits with nanosecond pulses, achieving up to 4.3× fewer shifts and significant energy savings.
• Advanced data placement strategies, including sequence-aware heuristics and genetic algorithms, optimize shift operations and overall performance across various RTM architectures.

Racetrack Memory (RTM) is an emerging class of non-volatile memory that stores information as a sequence of magnetic domains, primarily along the length of a nanowire, and moves these domains past fixed access ports for read and write operations. RTM targets ultra-high density comparable to tape storage, but with low latency random-access properties more typical of DRAM. The core innovation is the use of current-induced domain wall or skyrmion motion within the nanotrack as the fundamental mechanism for data access and movement, enabling area-efficient and low-leakage on-chip and embedded-memory architectures (Khan et al., 2019).

1. RTM Device Architecture and Physical Principles

An RTM cell consists of a ferromagnetic nanowire (nanotrack) subdivided into a series of discrete magnetic domains, each representing a single bit via their magnetization direction. These domains are separated by domain walls (DWs) or, in some variants, by the presence or absence of nanoscale spin textures known as skyrmions. Multiple nanotracks are grouped into a domain block cluster (DBC), where each bit of a word is mapped to a distinct parallel nanotrack for bit-interleaving. Fixed-position access ports—implemented as magnetic tunnel junctions (MTJs) or similar transducers—are sited along the track to enable read and write operations (Khan et al., 2019).

To access a given bit, the entire nanotrack is shifted so that the desired domain aligns beneath an access port. This shift is effected via a nanosecond-range current pulse, typically with per-shift costs of $t_{shift}\approx0.8$–$1.0~\mathrm{ns}$ and $E_{shift}\approx1.9$–$2.2~\mathrm{pJ}$ (Khan et al., 2019). The total access latency is

$$L_{access} = n_{shifts} \cdot t_{shift} + t_{read/write},$$

where $n_{shifts}=|i-j|$ for accessing domain $i$ from position $j$.

2. Shift Operations and Their Impact

The intrinsic requirement for shift operations introduces two principal challenges: significant variability and increase in access latency, and a dynamic energy overhead scaling with the number of shifts per access. Worst-case access latency can be an order of magnitude higher than for SRAM or DRAM, depending on domain positioning, while the dynamic shift energy can constitute the majority of RTM access energy. The per-access energy for cases where a fraction $f$ of accesses require one or more shifts is given by

$$E_{access} = E_{read/write} + f\,\bar n_{shifts}\,E_{shift},$$

where $\bar n_{shifts}$ is the mean shift count per access (Khan et al., 2019).

3. Data Placement Strategies for Shift Minimization

Data (variable) placement within RTM nanotracks has a first-order impact on overall performance and energy. Two subproblems are distinguished: intra-DBC placement (ordering variables on a track) and inter-DBC distribution (assignment of variables to clusters).

Earlier approaches focused on access-frequency heuristics, such as round-robin assignment across DBCs sorted by frequency (Access Frequency Distribution, AFD). This ignores the temporal ordering and liveliness (first and last usage) of variables, which can be suboptimal for access patterns encountered in practice—especially as the underlying RTM configuration (track length, DBC count, port count) varies (Khan et al., 2019).

4. Generalized Placement: Liveliness-Aware Heuristics and Genetic Algorithms

Recent work introduced generalized data placement strategies incorporating both access frequency and temporal liveliness, offering improved adaptability across RTM architectures (Khan et al., 2019):

Sequence-aware heuristic: This approach analyzes the lifespans of variables within the access sequence. Variables with disjoint lifespans can be co-placed in access order within the same DBC, such that maximal re-use minimizes inter-access shifts. The heuristic greedily selects variables to maximize the sum of access frequencies among those with non-overlapping intervals, assigning them to a minimal DBC set, and then using intra-DBC heuristics (e.g., access-graph permutations) for residual variables. This method runs in $O(|V|\log|V| + q|V|)$ and achieves up to a $3\times$ reduction in shifts versus frequency-ordering heuristics.

Genetic algorithm (GA) baseline: The data placement is also formalized as a combinatorial optimization problem, solved via a $(\mu+\lambda)$ GA with dedicated crossover and mutation operators to search the space of variable-to-DBC assignments (including intra-DBC permutation), with the objective of minimizing total shift cost over the input trace. This method serves as a near-optimal performance bound for heuristic assessment.

Mathematically, the placement is formalized as a binary assignment problem: $$\min_{\{x_{i,j}\}} \sum_{i,j} c_{i,j} x_{i,j},\quad \text{s.t.}~ \sum_j x_{i,j} = 1,~ x_{i,j}\in\{0,1\},$$ where $c_{i,j}$ is the shift cost for assigning variable $i$ to DBC $j$.

5. Experimental Validation and Quantitative Impact

All strategies were benchmarked using the OffsetStone suite and RTSim (cycle-accurate RTM simulator, 32 nm parameters) across a suite of RTM configurations (2–16 DBCs, 32 tracks per DBC, varying domains). The liveliness-aware heuristic yielded the following geometric-mean improvements across 30 traces and workloads (Khan et al., 2019):

• Number of shifts: Up to 4.3× reduction over AFD with best intra-DBC heuristic.
• Performance: 50–70% reduced average access latency at low-DBC configurations; overall runtime increased by 46%.
• Dynamic energy: Up to 77% reduction at 2 DBCs, 21% at 16 DBCs; average 55% total energy savings.

The heuristic and GA solutions were within 38% of random-walk lower bounds, supporting near-optimality claims.

Method	Shift Reduction	Runtime Gain	Energy Savings
Sequence-aware Heuristic + Intra-DBC	up to 4.3×	up to 46%	up to 55%
Baseline AFD	1×	baseline	baseline

6. Adaptability and Architectural Implications

Unlike earlier approaches, the sequence-aware heuristic is architecture-agnostic: it uses variable lifespans and frequency as input, and can be adapted as the number of access ports, track lengths, or DBC structures vary, provided the shift cost model and port-alignment rules are updated. Compiler integration is straightforward, as the method operates via trace-driven analysis without hardware modifications.

Trade-offs are architectural: increasing DBC count reduces intra-DBC shift counts, but increases leakage and area overheads due to added access ports. Empirical results identify 4–8 DBCs (for 4 KiB RTM) as optimal for energy-delay product. As capacity scales, optimization must balance packing disjoint variables (to minimize shifts) against DBC saturation effects.

7. Future Directions and Research Outlook

Future work may investigate multi-level variable lifeliness clustering or dynamic run-time re-placement to further exploit shifting patterns, particularly as RTM technology and compiler integration co-evolve. The reported gains—4.3× fewer shifts, 46% higher performance, and 55% lower energy—bring RTM-based memory architectures closer to practical, high-density, low-power on-chip deployments with DRAM-class latency and performance (Khan et al., 2019).