Quantum Data Centre Paradigm

• Quantum Data Centre Paradigm is a modular network connecting quantum processing units via reconfigurable optical networks to enable large-scale computation using entanglement and teleportation-based non-local gates.
• The architecture leverages diverse network topologies like Fat-Tree, Clos, QFly, and BCube, optimizing resource sharing, path diversity, and minimizing EPR generation delays to overcome single-device limitations.
• Benchmarking and cross-layer optimization reveal that flattened, low-hop networks with robust Bell-state measurement provisioning and low-loss optical switches are key to reducing distributed latency and enhancing overall performance.

A quantum data center (QDC) is a facility that interconnects multiple quantum processing units (QPUs) via a reconfigurable optical network to construct a large-scale, distributed quantum computer. The QDC paradigm is defined by its use of entanglement (@@@@4@@@@ pairs) and teleportation-based non-local gates to extend total logical qubit capacity beyond the constraints of any single physical QPU, while amortizing expensive photonic and measurement infrastructure across many modules (Pouryousef et al., 4 Jan 2026). QDCs fundamentally differ from classical data centers in their reliance on probabilistic entanglement, quantum memory coherence, and specialized scheduling to execute distributed quantum circuits. This article reviews the core architectural models, performance metrics, quantum-specific trade-offs, benchmarking results, and pragmatic recommendations as developed in systematic benchmarking studies.

1. Core Definition and Architectural Motivation

A QDC is a modular, networked system of QPUs, each hosted in a rack, linked by optical switches and fibers—augmented with photonic entanglement sources and Bell-state measurement (BSM) modules—to realize a distributed quantum computation fabric (Pouryousef et al., 4 Jan 2026). Unlike monolithic quantum processors, which are fundamentally limited by qubit count, wiring, and error rate scaling, QDCs partition quantum algorithms across multiple QPUs and implement “non-local” gates via entanglement-assisted teleportation. This enables:

• Scalability of logical qubit count, limited only by the network and control infrastructure.
• Deployment of near-term small- to medium-scale QPUs as functional components in a larger logical computer.
• Resource sharing and amortization of expensive photonic and BSM hardware across a large compute fabric.

The architectural principle is thus to overcome the scaling limitations of single devices by leveraging modularity and optics-based interconnect networks tailored to quantum information science.

2. Quantum Data Center Network Topologies

The design of QDCs revolves around several representative network architectures, each with distinct performance characteristics:

Fat-Tree

• Switch-centric three-layer (edge, aggregation, core) topology.
• Ensures full bisection bandwidth with high path diversity (~k² equal-cost paths for radix k).
• 4 maximum switch hops between QPUs; high symmetry (Pouryousef et al., 4 Jan 2026).

Clos

• Folded Clos (multi-stage non-blocking tree generalizing Fat-Tree).
• Decouples switch radix, rack fanout, and fabric size for precise scaling.
• Topology parameters (radix k, ToRs T, QPUs per ToR R) define hop count, path diversity.

QFly

• Flattened, low-diameter “Dragonfly” network with few high-radix switches and configurable global links.
• Path lengths as low as 2–3 hops (QFly_full) to 4–5 in sparse QFly variants.
• Tunable path diversity and resource concentration by varying k_ring (count of inter-switch connections).

BCube

• Server-centric, multi-layer design where QPUs serve as both computational modules and entanglement repeaters.
• L = k_bcube+1 layers, n^{k_bcube} switches per layer, provides up to L-hop paths.
• High path diversity from multiple independent repeater chains.

Each topology exhibits a trade-off between path length, resource utilization, switch count, and path diversity, fundamentally shaping quantum circuit latency and resource contention.

3. Quantum-Specific Performance Drivers

Distributed execution in a QDC exposes unique quantum hardware constraints not present in classical architectures:

• EPR-pair generation delay: Quantum communication is fundamentally probabilistic due to optical loss (in fibers, switches, BSMs, memories). The success probability for end-to-end EPR generation is $$p_\mathrm{gen}(L_\mathrm{tot})=10^{-L_\mathrm{tot}/10}$$ for total loss $L_\mathrm{tot}$ (in dB), with expected latency $T_\mathrm{EPR}=T_\mathrm{att}/p_\mathrm{gen}$ (Pouryousef et al., 4 Jan 2026).
• Coherence-limited retry window: In architectures employing quantum memories (e.g., BCube), all required entanglement segments in a multi-hop path must succeed within a coherence window $T_\mathrm{coh}$; otherwise, all are discarded and retried, causing exponential abort rates as path length increases.
• Resource contention: Limited BSM modules per switch, finite communication qubit ports, and blocking in optical paths introduce queuing for remote gates, increasing overall execution time.
• Switch reconfiguration latency: Optical switches incur delay when re-routing, which adds per-path overhead that accumulates for long or irregular circuit communication patterns.

The circuit execution latency $T_\mathrm{dist}$ is thus a function of stochastic EPR generation, resource contention, reconfiguration latency, and path diversity.

4. Mathematical Modeling of Latency and Capacity

Key models compute the quantum-specific bottlenecks in QDC operation:

• EPR generation delay: Given an end-to-end loss $L$ (dB), transmissivity $T_\mathrm{chan} = 10^{-L/10}$. Success probability for an EPR attempt is $p_\mathrm{gen}(L) = T_\mathrm{chan}$. The expected EPR setup latency is $$T_\mathrm{EPR}(L) = T_\mathrm{att}/p_\mathrm{gen}(L)$$.
• BCube coherence constraint: For $L$ segments, all must succeed within $T_\mathrm{coh}$. The retry window tightens as path length increases.
• Non-local gate latency: $$T_\mathrm{tele} = T_\mathrm{EPR} + T_\mathrm{BSM} + T_\mathrm{reconf} + T_\mathrm{comm}$$, with $T_\mathrm{BSM}$ the time per Bell-state measurement, $T_\mathrm{reconf}$ switch reconfiguration, $T_\mathrm{comm}$ communication delay (often negligible in short-distance networks).
• Scalability ratio: $$\rho_\mathrm{lat} = T_\mathrm{dist}/T_\mathrm{mono}$$, i.e., the ratio of distributed to monolithic circuit execution latency, directly quantifies the scaling penalty.

These models expose how topology, physical hardware characteristics, and resource provisioning interact to govern practical QDC throughput and latency (Pouryousef et al., 4 Jan 2026).

5. Benchmarking Results and Comparative Tradeoffs

Extensive benchmarking quantifies QDC performance for long-range workloads and contrasting provisioning models:

Fixed BSMs Per Switch (e.g., two per switch, N=128 QPUs):

Architecture	$\rho_\mathrm{lat}$ (long-range)
Clos_tight	~2.4
Fat-Tree	~2.6
QFly (k_ring=m/2)	~1.9
QFly (k_ring=k–m)	~1.6
QFly_full	~1.3
BCube ($\tau_\mathrm{cut}=200\,\mu$s, parallel)	~2.0

Fixed Global BSM Budget (e.g., 100 total):

Architecture	$\rho_\mathrm{lat}$ (long-range)
QFly_full	~1.2
QFly (k–m)	~1.4
BCube	~1.7
Clos, Fat-Tree	~2.3–2.5

These results demonstrate that flattened, high-radix switch networks (QFly variants with large $k_\mathrm{ring}$) consistently achieve lower distributed latency, especially under global BSM constraints. Deep, multi-stage networks (Fat-Tree, Clos) are highly sensitive to BSM contention and optical loss, suffering larger increases in $\rho_\mathrm{lat}$. Server-centric, memory-intensive BCube degrades rapidly under short coherence time ($\tau_\mathrm{cut}$) regimes.

Path-length distributions confirm that high-hop-count paths accumulate latency and failure probabilities, with switch-centric designs “saturating” at ~6+ hops for large N.

6. Interactions and Cross-Layer Optimizations

Performance is not governed solely by network topology; strong cross-layer interactions determine end-to-end behavior:

• Optical-switch insertion loss compounds multiplicatively per hop. High-hop-count networks experience severe loss penalties, reducing $p_\mathrm{gen}$ and increasing EPR setup time. Low-hop, flat topologies (QFly, low-diameter BCube) are less sensitive.
• Switch reconfiguration costs must be amortized by batching circuit communication where possible; architectures with high path reuse perform best.
• BSM Provisioning needs careful alignment to expected non-local gate rate and switch count. Switch-rich fabrics (many small switches) are BSM-starved unless BSMs per switch scale proportionally.
• Scheduling policy design is critical. Sequential vs. parallel scheduling in BCube, dynamic vs. static scheduling in generic QDCs, and adaptive lookahead in presence of coherence limitations can each yield $\sim2-3\times$ improvement in latency or throughput when matched to hardware constraints.

An optimal QDC emerges only through co-optimization of topology, hardware insertion loss, BSM capacity, coherence time, and scheduling algorithms.

7. Design Recommendations and Practical Guidelines

Pouryousef et al. (Pouryousef et al., 4 Jan 2026) provide quantitative guidance distilled from simulation and modeling:

• BSM provisioning: Increase per-switch BSMs or employ global pools to match expected resource contention. Under-provisioning restricts throughput.
• Topology choice: Prefer QFly variants with high $k_\mathrm{ring}$ for communication-intensive workloads; avoid deep hierarchical fabrics (Clos, Fat-Tree) unless extremely low optical loss and abundant BSM resources are available.
• BCube operation: Implement parallel swap scheduling, and ensure $T_\mathrm{coh}$ is significantly greater than typical entanglement setup time to reduce failure rates.
• Switch hardware: Prioritize optical switches with both low insertion loss and fast reconfiguration. Loss is especially critical in multi-stage designs.
• Cross-layer orchestration: Expose physical-layer parameters (coherence time, reconfiguration latency, insertion loss) at the software orchestration level, enabling partitioning, routing, and hardware tuning to be jointly selected for each workload pattern.

In summary, the quantum data center paradigm is shaped by nontrivial, topology-dependent interplay of quantum-specific effects—probabilistic entanglement, EPR distribution, memory coherence, and photonic resource contention. Systematic benchmarking reveals that scalable and high-performance QDCs require joint architectural, hardware, and scheduling optimization, with flattened, few-hop topologies and robust BSM provisioning emerging as central design principles for near-optimal distributed quantum computation (Pouryousef et al., 4 Jan 2026).