Distributed Quantum Circuit Latency

• Distributed quantum circuit execution latency is the total wall-clock time to complete a partitioned quantum computation across interconnected processors, encompassing gate execution, communication overhead, and synchronization delays.
• Latency models combine local gate times, remote swap penalties, entanglement delays, and classical control overheads to offer quantitative metrics for optimizing distributed quantum systems.
• Optimization techniques, including ILP, evolutionary algorithms, and reinforcement learning-based scheduling, can reduce latency by up to 35-70%, balancing fidelity and execution speed.

Distributed quantum circuit execution latency is the total wall-clock time required to complete a quantum computation when the circuit is partitioned across multiple quantum processors, each with distinct hardware constraints and interconnected via communication channels of nontrivial fidelity and latency. The metric encapsulates quantum gate execution times, inter-processor synchronization, entanglement generation or teleportation delays, classical control overheads, and any qubit idling arising from distributed control or protocol requirements. This latency fundamentally limits the scalability and practical utility of quantum algorithms in both error-corrected and near-term quantum computing. The following sections enumerate core principles, latency models, optimization techniques, and the influence of hardware, network, and scheduling choices as established in recent literature.

1. Latency Model Foundations: Quantum Gate, Communication, and Control Layers

Execution latency in distributed quantum circuits is governed by the superposition of several components: local gate execution time, remote-gate communication overheads, synchronization and scheduling delays, classical processing latency, and qubit coherence constraints. A representative latency equation aggregates these aspects: $$T_{\text{exec}} = \sum_{g \in G_{\text{local}}} t_g + \sum_{\text{swaps}} t_{\text{swap}} + \sum_{\text{EPs}} L_{\text{ent}} + \text{wait}_{\text{overheads}}$$ where $G_{\text{local}}$ is the set of gates local to each QPU, $t_g$ denotes single- or two-qubit gate time, swaps compensate for limited native connectivity, and $L_{\text{ent}}$ models entanglement-pair (EP) generation and consumption latency for non-local gates (Sundaram et al., 2024).

Distributed control architectures, e.g., Distributed-HISQ, introduce additional latency through synchronization between independent control boards. Protocol design—such as the Booking-Based Instruction Synchronization Protocol (BISP)—can mask link latency $L_{ij}$ behind deterministic quantum operations, potentially achieving zero-cycle synchronization overhead when local pipeline gaps $D_i$ exceed communication times (Zhao et al., 5 Sep 2025).

In surface-code-protected architectures, total reaction time per logical event further incorporates classical decoder latency,

$$T_{\text{reaction}} \equiv \gamma_{\text{mem}} = 6 d \tau_d(d^2) + t_{\text{com}}$$

where $\tau_d(N)$ scales polynomially with code distance $d$ and $t_{\text{com}}$ is controller–orchestrator delay. This reaction latency impacts both runtime and required physical qubit overhead due to extended idling (Khalid et al., 13 Nov 2025).

2. Quantum Communication Latency: Physical and Topological Determinants

Quantum-link latency is a critical bottleneck for distributed gate operations. Its constituent terms include propagation delay, entanglement-generation time, purification rounds, classical signaling, and pulse sequencing latency. For a link $d$ of velocity $v$,

$T_{\text{prop}} = \frac{d}{v}$

$$T_{\text{gen}} = \frac{T_{\text{slot}}}{P_{\text{succ}}}, \;\; P_{\text{succ}} = \eta e^{-\alpha d}$$

with $T_{\text{slot}}$ as setup plus propagation, $\eta$ conversion efficiency, and $\alpha$ attenuation (Rached et al., 13 May 2025).

Network topology heavily impacts these latencies: path length $h$ (in inter-QPU hops), number of switches, and resource contention at Bell state measurement (BSM) units are modeled by

$$\mathbb{E}[T_{\text{pair}}](h) = \frac{T_{\text{src}} + 2h\ell/v_{\text{fiber}} + T_{\text{reset}}}{10^{- (\alpha h\ell + h L_{\text{sw}}(k) + L_{\text{BSM}})/10}}$$

$$T_{\text{tele}} = \mathbb{E}[T_{\text{pair}}] + T_{\text{BSM}} + T_{\text{cc}} + T_{\text{local}}$$

Resource contention at switches (BSM queueing) adds

$$T_{\text{cont}} \simeq \left\lceil \frac{N_{\text{req}}}{b} \right\rceil T_{\text{BSM}}$$

with $N_{\text{req}}$ concurrent requests and $b$ BSM units per switch (Pouryousef et al., 4 Jan 2026).

Adoption of dense wavelength division multiplexing (DWDM) and reconfigurable quantum interfaces (RQIs) can raise Bell-pair distribution rates from kHz to MHz, lowering per-gate communication time to sub-$\mu$s and reconfiguration delay to the ns scale (Zhao et al., 7 Apr 2025).

3. Scheduling and Mapping Algorithms for Latency Minimization

Latency-centric scheduling of distributed quantum circuits leverages graph partitioning, job-shop scheduling, combinatorial optimization (ILP/MILP, simulated annealing), and evolutionary approaches. The NoTaDS framework employs ILP to simultaneously minimize makespan $L$ and maximize overall fidelity $F = \sum_{ij} f_{ij} X_{ij}$. Constraints enforce one-to-one assignment of subcircuits, time budgets, device sequencing, and communication deadlines: $$\forall\,i: \sum_j X_{ij} = 1, \quad \forall\,j: \sum_i d_i X_{ij} + \sum_{i,i'} \delta_{ii'} (X_{ij} + X_{i'j}) \leq \tau_j$$ Matching-based graph algorithms provide polynomial-time solutions when the number of subcircuits does not exceed available QPUs (Bhoumik et al., 2023).

Evolutionary algorithms and simulated annealing optimize both qubit placement and circuit transformation to reduce non-local interaction weight, achieving up to 35% latency reduction over static partitioning. Solver complexity scales polynomially in evaluated mappings and schedule space (Sünkel et al., 15 Jul 2025).

In resource-constrained architectures, MILP formulations co-optimize allocation of circuits to QPUs, reduce remote-gate infidelity, and tune batch sizes to control latency-under-contention (Bahrani et al., 2024).

Compiler backends employing reinforcement learning via Double Deep Q-Networks learn near-optimal policies for EPR pair generation, remote operation scheduling, and SWAP injection, yielding 40%–70% speed-up in simulation settings for decoherence-limited circuits (Promponas et al., 2024).

4. Circuit Partitioning and Cutting: Fidelity-Latency Trade-offs

Circuit cutting is extensively used to partition large circuits into executable subcircuits, thereby reducing noise but introducing classical communication and postprocessing overhead. The cut model manifests a convex Pareto frontier:

• Fewer cuts minimize recombination latency and shot overhead,
• More cuts yield higher fidelity and parallelization but expedite classical postprocessing requirements and data transfer.

With cut+NoTaDS scheduling, a cut 10-qubit circuit demonstrates a fidelity improvement of 21.2% and a makespan reduction of 42% compared to uncut execution on the best device. For $K$ cuts, classical postprocessing time and the number of recombined measurement outcomes scale as $4^K$, guiding practical cut thresholds to $K \leq 4$ (Bhoumik et al., 2023).

Recent wire-cut protocols, as deployed in deadline-aware frameworks, reduce the sampling blow-up per cut from 16 to 9 subcircuits, bringing net makespan reductions of 25% under shot- and dependency-aware schedules (Dehaini et al., 4 Dec 2025).

5. Data Center Architecture, Topology, and Scalability

Quantum data center architectures such as QFly, BCube, Clos, and Fat-Tree exhibit unique latency profiles in modular DQC, contingent on path diversity, switch loss, memory decay, and BSM sharing policies. The expected EPR-pair generation latency strongly depends on the product of the total link loss and network segment count: $$T_{\mathrm{att}} = T_{\mathrm{src}} + \frac{2D}{v_{\mathrm{fiber}}} + T_{\mathrm{reset}},\quad T_{\mathrm{chan}} = 10^{-L_{\mathrm{tot}} / 10},\quad \mathbb{E}[T_{\mathrm{pair}}] = T_{\mathrm{att}} / T_{\mathrm{chan}}$$ for a path of length $D$ with cumulative loss $L_{\mathrm{tot}}$ (Pouryousef et al., 4 Jan 2026).

Performance measurements across workloads with varied locality and circuit depth show:

• Clos and Fat-Tree topologies yield the lowest distributed/monolithic latency ratios under sufficient BSM per switch,
• QFly architectures are preferable under global BSM constraints due to reduced switch count and path length,
• High-loss regimes (in switches or fiber) amplify latency for deep-fabric architectures,
• Protocol-level optimizations (parallel swap, increased $\tau_{\text{cut}}$) mitigate memory loss in BCube-style server-centric chains.

Holistic architectural design requires joint consideration of topology, resource scheduling, physical-layer parameters, and gate-mapping policies to ensure low-latency execution.

6. Experimental Benchmarks, Simulation, and Practical Considerations

Latency scaling is exponential in qubit count and circuit complexity under classical simulation methods. Full-circuit execution on distributed GPU memory (as in Qiskit-Aer-GPU) yields latency $\Theta(2^N/P)$ for $N$ qubits and $P$ nodes. Circuit partitioning (CutQC) benefits scenarios with constrained per-node memory, but classical postprocessing overhead $O(4^K 2^N)$ dominates for large cut count $K$. Benchmarks confirm that, for $N \leq 34$, full-circuit simulation is $10\times$–$100\times$ faster than circuit-splitting if adequate memory is available per node (Sarode et al., 17 Feb 2025).

Static Timing Analysis (STA) and task reordering can reduce idle time in distributed implementations of Shor’s algorithm by 50% or more for neutral-atom platforms, with channel-pipelining strategies balancing depth and resource efficiency across architecture types (Schmidt et al., 28 Mar 2025).

7. Future Directions and Open Challenges

Achieving lower distributed execution latency will sustain advances in high-fidelity quantum networking, low-overhead synchronization, scalable scheduling, and error correction codes with large $\Lambda$. MHz-rate Bell-pair delivery and ns-level reconfiguration (as in RQI+DWDM platforms) remove network bottlenecks for fault-tolerant distributed algorithms. End-to-end pipeline optimization, including dynamic routing, dependency-aware scheduling, multi-path entanglement generation, and real-time resource mapping across heterogeneous hardware, are poised to shape future modular quantum computing systems (Zhao et al., 7 Apr 2025).

Continual co-design among quantum architectures, control strategies, and compiler stack will be required to maximize performance under realistic noise, fidelity, and resource limitations. As decoherence budgets, entanglement throughput, and scaling constraints interact in nontrivial fashions, distributed quantum circuit execution latency remains a central metric dictating the boundaries of practical quantum computation.