Quantum-Classical Hybrid Framework

• Quantum-Classical Hybrid Framework is a computational paradigm that partitions complex quantum circuits into manageable subcircuits executed on quantum processors and merged via classical post-processing.
• It employs automatic circuit cutting with mixed-integer programming and states-merging to control quantum resource usage and reduce the exponential memory demands of full amplitude storage.
• The framework leverages tensor network contraction heuristics to scale effectively, demonstrating significant speedups and lower quantum hardware requirements in benchmark tests.

A quantum-classical hybrid framework constitutes a rigorously defined computational paradigm that orchestrates the interaction between quantum processors (quantum processing units, QPUs) and classical computational resources to solve algorithmic tasks surpassing the scale or fidelity of purely quantum or purely classical approaches. Distinct from mean-field or semi-classical architectures, modern frameworks such as ScaleQC implement principled integration mechanisms: partitioning large-scale quantum circuits into hardware-feasible subcircuits, executing these decomposed quantum units on modest QPUs, and reconstructing global solutions through advanced classical post-processing, often leveraging tensor network contraction and recursive state-merging. This enables the execution of quantum algorithms on currently available quantum hardware whose qubit count and coherence are insufficient for monolithic quantum circuits, while controlling classical computational overheads and memory consumption (Tang et al., 2022).

1. Hybrid Architectural Design and Workflow

Hybrid computation in the ScaleQC framework is realized through a sequential, tightly-coupled workflow partitioned into three key phases:

• Automatic circuit cutting: The input quantum circuit $C$ is partitioned into $n_C$ subcircuits $\{C_1,\ldots,C_{n_C}\}$ via the solution of a load-constrained mixed-integer program (MIP). Each subcircuit is bounded by a two-qubit gate load parameter $\alpha$, ensuring compatibility with the available QPU resources.
• Quantum execution of subcircuits: Each subcircuit $C_i$ is executed on QPUs across all bin assignments generated by the states-merging framework. Inputs and measurements employ the Pauli basis, maximizing compatibility with standard quantum hardware initialization and measurement protocols.
• Classical post-processing (tensor network contraction & states-merging): Quantum outputs (e.g., probability vectors) from all subcircuits and all basis assignments are combined to reconstruct a global amplitude vector or some reduced representation thereof. This is achieved without explicit storage of exponentially large state spaces, employing tensor contraction heuristics and recursive binning.

Workflow schematic (from Algorithm 1):

1. SolveCuts(C, α) → {C₁,…,Cₙ_C}, compute graph G 2. Initialize priority queue L ← ∅, recursion counter r←0 3. while r<R do 4. if r>0 and no bin to expand then break 5. AssignBins ← StatesAssignment(r, current_bin, M, {n_i}) 6. // QPU: run each subcircuit C_i under each bin assignment → p_{i,k} 7. T ← ContractComputeGraph(G, {p_{i,k}}) 8. Update L with top-R bins from T 9. current_bin ← ExtractTop(L) 10. r ← r+1 11. end while 12. return collected solution states

2. Quantum States Merging: Subspace Binning

ScaleQC introduces a quantum states merging mechanism to bypass the $\mathcal{O}(2^n)$ memory bottleneck associated with explicit amplitude vector storage:

For a circuit partitioned into $n_C$ subcircuits of sizes $n_i$ and $K$ cuts, each subcircuit $i$ under basis assignment %%%%10%%%% outputs $p_i(k)\in\mathbb{R}^{2^{n_i}}$. The full circuit state is

$$P = \sum_{k=1}^{4^K} \bigotimes_{i=1}^{n_C} p_i(k) \in \mathbb{R}^{2^n}$$

States merging recursively groups basis states into $L$ bins (indexed by $B_j$) and tracks bin sums:

$q_j = \sum_{x\in B_j} P[x], \quad j=1,\ldots,L$

High-amplitude bins are split recursively (“top-R search”) until singleton states or maximum recursion $R$ is reached. Throughout, memory usage is bounded by $O(M)$ and QPU resources scale only with subcircuit sizes, not the global qubit count. The states-assignment algorithm controls bin width and recursion tree depth using dynamic partitioning formulated to limit $L\leq M$.

3. Automatic Circuit Cutting via Mixed-Integer Programming

The circuit cutting phase utilizes a rigorous MIP formulation. Each two-qubit gate in the DAG $(V,E)$ is assigned or cut according to binary variables $x_{e,c}$ and $y_{v,c}$. The objective is to minimize the maximal subcircuit degree $L$ under:

• Subcircuit load constraint: $S_c \leq \alpha |V|$
• Assignment and consistency constraints
• Edge cut and gate placement variables

The formal optimization problem is:

$$\begin{align} \text{minimize } & L \ \text{s.t. } & I_c + O_c \leq L, \forall c \ & S_c \leq \alpha|V|, \forall c \ & \sum_c y_{v,c}=1, \forall v \ & \sum_c x_{e,c}=1, \forall e \end{align}$$

Solution employs commercial solvers (e.g., Gurobi) and ensures every subcircuit respects the QPU's two-qubit gate budget.

4. Tensor Network Contraction and Classical Compute Graphs

Post-cut, the reconstruction of global amplitudes or marginal probabilities is performed using tensor network techniques. Each subcircuit output forms a tensor $T_i$ of shape $$(d_{i,1}\times\ldots\times d_{i,r_i}\times 2^{n_i})$$ where $d_{i,j}=4$ per cut edge, following the compute graph $G$. The network contraction cost for merging tensors $A,B$ over shared indices $J$ is:

$$\mathrm{Cost}(A\star_J B) = O\left(\prod_{k\in A\cup B} \mathrm{dim}(k)\right)$$

Optimal contraction order search is NP-hard; ScaleQC uses the CoTenGra heuristic to minimize intermediate memory and floating point operations. Slice-based subtasking ensures all intermediate tensors fit in available RAM.

Total floating point operations:

$$F = \sum_{t=1}^s \prod_{k\in\mathrm{indices}_t} \mathrm{dim}(k)$$

5. Quantitative Benchmarks and Resource Analysis

Experimental benchmarks demonstrate advantages in both quantum resource utilization and classical computational runtime.

Table: Representative performance (Cut_M benchmark, states-merging regime $\alpha$, $M=2^{20}$, $R=n/20$)

Circuit	Qubits	Cut_M Time (s)	Recursions	Max Subcircuit Qubits	QPU Area Ratio (%)
QAOA-Erdos	80	420	4	50	57
Supremacy	144	820	7	85	83
BV	1000	1600	50	250	25

Runtime scales nearly linearly with qubit count under states-merging, in contrast to the exponential saturation of full classical simulation. For sample generation tasks, ScaleQC with a single GPU+CPUs achieves $\sim$7x speedup and reduces physical QPU requirements to $\sim$25–80% of a full quantum platform (Tang et al., 2022).

6. Scalability, Limitations, and Practical Boundaries

The scalability of hybrid frameworks is dictated by:

• Memory reduction: States-merging yields $O(M)$ complexity versus $O(2^n)$ for direct amplitude storage, supporting circuits up to 1000 qubits under aggressive binning.
• Post-processing complexity: Tensor contraction is tractable for maximum compute-graph degrees $\leq$15 using slicing; further parallelization or distributed implementations are required for larger instances.
• Circuit cutting bottleneck: MIP cut search time grows with circuit scale; specialized or streaming heuristics are an avenue for future work.
• Flat amplitude landscapes: The states-merging assumes most amplitudes are concentrated in few solution states. Circuits with nearly uniform output distributions (e.g., high-depth random circuits) may necessitate alternative sampling or reconstruction methods.
• Heuristic contraction ordering: No guaranteed optimality; performance may deteriorate for adversarial graphs.

In conclusion, quantum-classical hybrid frameworks such as ScaleQC enable practical computation on near-term quantum hardware, overcoming qubit and coherence constraints by delegating large entanglement management and amplitude recovery to classical post-processing engines, while precisely controlling quantum resource budgets and runtime (Tang et al., 2022).