Passive Matrix Addressing in Memory Crossbars

• Passive matrix addressing is a technique that utilizes intersecting word and bit lines with passive, two-terminal junctions to electrically select and program individual cells.
• The V/2 and V/3 biasing protocols minimize sneak-path currents by assigning differentiated voltages, enhancing readout fidelity and easing programming challenges.
• Key challenges include nonlinear device physics, voltage-drop imbalances, and device variability, which demand optimized biasing, iterative tuning, and advanced selector designs.

Passive matrix addressing is a scheme employed in high-density device arrays—such as memristive and phase-change memory crossbars—to enable the electrical selection, readout, and programming of individual cells without the presence of per-cell active elements like select transistors. This approach is foundational to “1D1R” (one-diode–one-resistor) and “1R” (resistive only) architectures, achieving maximal density by crossing vertical and horizontal lines with only passive, two-terminal junctions at each intersection. While passive matrix addressing offers scaling benefits critical for neuromorphic computing and analog memory, it is fundamentally limited by sneak-path currents, nonlinear device physics, voltage-drop imbalances, and device variability, all of which impose distinct challenges and define the operational regime and achievable fidelity of such arrays (Noori et al., 2019, Kim et al., 2019).

1. Crossbar Array Architecture and Passive Addressing Protocols

A passive crossbar array forms the basis for this addressing technique: $m$ word lines (WLs) intersect $n$ bit lines (BLs), with each crosspoint containing a memory cell. In 1D1R and 1R arrays, these are realized by memristors (or phase-change resistors), with optional series diodes to enhance nonlinearity and block undesired leakage. No select transistor is present per cell, increasing spatial density and enabling integration of $>10^4$ cells per array (Noori et al., 2019, Kim et al., 2019).

To target a single cell $(p, q)$ during read or program, external drivers impose a selective voltage protocol. The classical “V/2” scheme assigns:

• $WL_p = +V_{sel}$, $BL_q = 0$
• all other $WL_{i\neq p} = +V_{sel}/2$, all other $BL_{j\neq q} = +V_{sel}/2$

This constrains the target device to experience $\pm V_{sel}$, half-selected devices $\pm V_{sel}/2$, and unselected devices ideally near zero net voltage. More advanced “V/3” protocols further distribute line potentials, reducing effective sneak-path contributions (Kim et al., 2019).

2. Device and Array-Level Electrical Behavior

Memristor devices in passive arrays exhibit non-ideal, nonlinear current–voltage (I–V) relations, further complicated by threshold switching. At small read biases (e.g., $n$0V), individual cells respond as $n$1 with dynamic range $n$2A$n$3pA (Kim et al., 2019). Higher biases reveal nonlinearity, quantified by $n$4. Programming exploits this nonlinearity with pulses exceeding stochastic thresholds, typically $n$5, $n$6 (Kim et al., 2019).

At the array level, Kirchhoff’s laws are used to model static DC operation. Each current path is decomposed as $n$7, where $n$8 is the small-signal conductance. This results in a block-sparse matrix equation,

$n$9

jointly encoding all node voltages, conductances, line resistances, and imposed boundary currents. The nonlinear diode selector, if present, requires each $>10^4$0 to satisfy a transcendental equation involving the Lambert-W function:

$>10^4$1

with $>10^4$2 the reverse saturation current, $>10^4$3 the ideality factor, $>10^4$4 the thermal voltage, and $>10^4$5 the resistance (Noori et al., 2019).

3. Sneak-Path Currents and Mitigation

Passive matrix arrays are fundamentally limited by sneak paths—unintended conductive routes through half-selected or unselected devices—which contribute parasitic current, obscure readout, and cause unintentional programming. For V/2 biasing, the measurable current for a selected cell is:

$>10^4$6

If nearly all half-selected conductances are $>10^4$7 and the array dimension is $>10^4$8, the sneak contribution,

$>10^4$9

becomes non-trivial for large $(p, q)$0 or low $(p, q)$1, limiting achievable selectivity (Kim et al., 2019).

Sneak-path mitigation employs advanced biasing:

• V/2 scheme: Reduces off-target voltages to half the selection voltage, scaling parasitic current as $(p, q)$2.
• V/3 scheme: Distributes potentials so half-selected and unselected devices experience even lower biases, cutting sneak current by a further $(p, q)$3 relative to V/2 (Noori et al., 2019, Kim et al., 2019).
• Nonlinear selectors: Use of 1D1R stacks, where diode-like selector nonlinearity ensures exponentially lower conductance at non-selected biases.

4. Device Variability, Error Propagation, and Addressing Accuracy

Device-to-device variability, especially in switching thresholds ($(p, q)$4, $(p, q)$5 in $(p, q)$6 arrays) and conductance response, impacts both programmability and read reliability. The stochastic distribution of $(p, q)$7 affects the probability that any given programming pulse yields the desired conductance increment, modelled as

$(p, q)$8

where $(p, q)$9 is the cumulative normal distribution (Kim et al., 2019).

For analog-grade applications, tuning algorithms implement incremental write-verify cycles, each pulse followed by a conductance readout, using feedback to bring post-pulse deviation below preset windows (e.g., $WL_p = +V_{sel}$0). Empirically, $WL_p = +V_{sel}$1 of devices in a $WL_p = +V_{sel}$2k device array converge within $WL_p = +V_{sel}$3 absolute error after three programming cycles, despite threshold fluctuations (Kim et al., 2019).

5. Scalability, Line Resistance, and Biasing Strategies

The limits of passive matrix addressing are inevitably set by array size, line resistance, and biasing symmetry:

• Line resistance ($WL_p = +V_{sel}$4): Increasing $WL_p = +V_{sel}$5 (e.g., from $WL_p = +V_{sel}$6 to $WL_p = +V_{sel}$7 per line segment in a $WL_p = +V_{sel}$8 array) causes voltage nonuniformity, raises effective $WL_p = +V_{sel}$9 for ON states, and lowers the sense margin ($BL_q = 0$0) (Noori et al., 2019).
• Array size: Scaling from $BL_q = 0$1 to $BL_q = 0$2 exponentially increases numbers of half-selected paths and reduces the margin between ON/OFF states, with sense margin falling by an order (Noori et al., 2019).
• Sense resistor ($BL_q = 0$3): Optimal $BL_q = 0$4 balances signal amplitude and Johnson–Nyquist noise (Noori et al., 2019).
• Biasing: Single-edge drive leads to highly uneven current distribution, whereas dual-side biasing and grounding flatten currents, equalizing cell heating and minimizing voltage offsets across the array (Noori et al., 2019).

Simulation-based guidelines suggest maintaining $BL_q = 0$5, using V/3 biasing, optimizing selector parameters ($BL_q = 0$6A, $BL_q = 0$7), and employing dual-end biasing to ensure scalability beyond $BL_q = 0$8 devices without catastrophic sense margin loss (Noori et al., 2019).

6. Programming Algorithms, Neuromorphic Applications, and Measured Performance

The efficacy of passive matrix addressing underlies applications such as analog neuromorphic computing. Using incremental-step write-verify routines, the $BL_q = 0$9 “4K-Memristor Analog-Grade Passive Crossbar Circuit” was programmed to grayscale levels $WL_{i\neq p} = +V_{sel}/2$0S at $WL_{i\neq p} = +V_{sel}/2$1V, with $WL_{i\neq p} = +V_{sel}/2$2 of devices within $WL_{i\neq p} = +V_{sel}/2$3 of target value after three tuning cycles (Kim et al., 2019). Multi-cycle re-tuning mitigates half-select drift.

As a demonstration, the array directly realized a single-layer perceptron for MNIST digit classification. Input voltages (downsampled pixels) were mapped to array columns; pre-trained weights were imported as cell conductances. Classification accuracy of $WL_{i\neq p} = +V_{sel}/2$4 (hardware, $WL_{i\neq p} = +V_{sel}/2$5 below software) was achieved with $WL_{i\neq p} = +V_{sel}/2$6 tuning error, confirming that V/2 addressing, multi-pass tuning, and careful biasing robustly support inference in practical tasks. Performance degrades gracefully as weight import error rises, sustaining operation even at $WL_{i\neq p} = +V_{sel}/2$7 perturbation with only minor accuracy drop (Kim et al., 2019).

7. Summary of Key Equations, Concepts, and Design Guidelines

Passive matrix addressing in high-density resistive memory crossbars is governed by a set of core equations and operational guidelines:

Equation / Concept	Expression / Range
Cell current (Lambert-W form)	$WL_{i\neq p} = +V_{sel}/2$8
Sneak-path current, V/2 scheme	$WL_{i\neq p} = +V_{sel}/2$9
Sense margin	$BL_{j\neq q} = +V_{sel}/2$0; $BL_{j\neq q} = +V_{sel}/2$1
Optimal selector parameters	$BL_{j\neq q} = +V_{sel}/2$2A, $BL_{j\neq q} = +V_{sel}/2$3 (for V/3 biasing)
Tuning error (empirical)	$BL_{j\neq q} = +V_{sel}/2$4 after 3 cycles in $BL_{j\neq q} = +V_{sel}/2$5k devices
Array scaling (reported)	>$BL_{j\neq q} = +V_{sel}/2$6–$BL_{j\neq q} = +V_{sel}/2$7 devices possible with proper line resistance control

Design optimization relies on combining advanced biasing (e.g., V/3), selector nonlinearity, minimized line resistance, symmetric drive schemes, and iterative, feedback-based programming. These techniques support robust, analog-grade operation even in the presence of material and device-level stochasticity, confirming the viability of passive matrix addressing for next-generation neuromorphic and memory devices (Noori et al., 2019, Kim et al., 2019).