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Parcae Architecture Overview

Updated 16 April 2026
  • Parcae Architecture is a suite of computational frameworks that optimize resource utilization, stability, and locality using innovations in quantum, DNN, and LLM systems.
  • It introduces constructive plaquette compilation, liveput-optimized DNN training, and looped language model stability to systematically address computational bottlenecks.
  • These methods enforce locality, enhance throughput, and provide robust scaling with theoretical guarantees, making them valuable for advanced system design.

Parcae Architecture encompasses a suite of distinctive computational frameworks developed independently but sharing the common objective of optimizing underlying resource utilization, stability, or locality in large-scale computational and physical systems. Recent research describes three principal areas of Parcae Architecture: (1) constructive plaquette compilation in quantum optimization, (2) liveput-optimized DNN training under preemption, and (3) stable scaling laws for looped LLMs. Each instantiation introduces rigorously defined models and algorithmic advances to address bottlenecks in its respective field.

1. Constructive Plaquette Compilation in the Parity Architecture

The Parcae, or “parity-in-plaquettes,” architecture targets the explicit implementation of higher-order Ising models and constrained spin-glass Hamiltonians using local interactions arranged on a 2D plaquette lattice.

A logical problem is formulated as an NN-spin Ising Hamiltonian with up to kk-body terms,

Hlogical=iJiσz(i)+i<jJijσz(i)σz(j)+i<j<Jijσz(i)σz(j)σz()+H_{\rm logical} = \sum_{i}J_i\,\sigma_z^{(i)} + \sum_{i<j}J_{ij}\,\sigma_z^{(i)}\sigma_z^{(j)} + \sum_{i<j<\ell}J_{ij\ell}\,\sigma_z^{(i)}\sigma_z^{(j)}\sigma_z^{(\ell)} + \dots

with optional polynomial side-constraints. The parity mapping introduces one physical qubit for each nonzero logical term, resulting in a lifted Hilbert space requiring enforcement of MNM-N independent parity constraints (where MM is the number of physical qubits). Qubits are placed on faces and vertices of a 2D rectangular grid, forming the “plaquette lattice,” and all interactions are local nearest-neighbor XORs over triples (triangles) or quadruples (squares).

A fully constructive algorithm incrementally builds the plaquette rectangle layer by layer. The space of constraints is computed using Gaussian elimination to produce a binary matrix CC in F2(MN)×M\mathbb{F}_2^{(M-N)\times M}. Constraints are successively decomposed into boundary-only forms and realized as explicit plaquette arrangements using deterministic strategies and ancilla qubit insertion. Each added plaquette increases the dimension of the enforced constraint space by one, ensuring all and only the necessary parity constraints are implemented. The flexibility of this scheme extends to incorporating hard side-constraints by preliminary placement of interacting qubits and guarantees locality for operations such as exchange drivers. Concrete examples demonstrate ancilla minimization and the enforcement of multibody constraints in layouts for four- and six-spin instances (Hoeven et al., 2023).

2. Proactive, Liveput-Optimized DNN Training under Preemptible Instances

Parcae presents a system for training deep neural networks (DNNs) cost-effectively on preemptible (spot) cloud instances, introducing key algorithmic and metric innovations to improve robustness and throughput. Unlike reactive systems that respond only after preemption events, Parcae forecasts future GPU availability and optimizes “liveput”—a metric denoting the expected training throughput under all possible preemption scenarios.

Time is divided into intervals of length TT, and the system predicts the total available GPUs (Ni,,Ni+I1)(N_i,\dots,N_{i+I-1}) using models such as ARIMA for practical accuracy and cost trade-offs. Monte Carlo preemption sampling then estimates possible topological GPU losses in the training setup. The liveput metric is quantified as

Liveput(D,P,V)=EvV[Throughput(Dv,Pv)],\mathrm{Liveput}(D,P,\mathcal V) = \mathbb{E}_{\vec v\sim\mathcal V}\left[\,\mathrm{Throughput}(D_{\vec v},P_{\vec v})\,\right],

where kk0 and kk1 enumerate data-parallel pipelines and pipeline depth, respectively, and kk2 describes a sampled preemption pattern. The liveput optimizer selects parallelization strategies over each lookahead window to maximize expected committed samples, extending liveput by considering migration overhead.

Migration is handled with three levels of (intra-, inter-stage, and full pipeline) adaptation, minimizing state transfer and leveraging stochastic invariance in micro-batch order. At each interval, Parcae re-optimizes its configuration and directs agents to enact efficient migration, with decisions informed by up-to-date forecasts. Empirical results demonstrate up to kk3 speedup over checkpoint-only and redundancy-based baselines and robustness within kk4 of an oracle solution (Duan et al., 2024).

3. Stable, Looped LLM Architectures and Scaling Properties

The Parcae looped architecture formulates the propagation of network states as a nonlinear time-variant dynamical system on the residual stream. Given token inputs kk5, the system computes embeddings kk6 and iterates the hidden state

kk7

over kk8 steps, with kk9 denoting the nonlinear contributions of recurrent sub-blocks minus the linear part.

Linearization yields a discrete-time LTI model Hlogical=iJiσz(i)+i<jJijσz(i)σz(j)+i<j<Jijσz(i)σz(j)σz()+H_{\rm logical} = \sum_{i}J_i\,\sigma_z^{(i)} + \sum_{i<j}J_{ij}\,\sigma_z^{(i)}\sigma_z^{(j)} + \sum_{i<j<\ell}J_{ij\ell}\,\sigma_z^{(i)}\sigma_z^{(j)}\sigma_z^{(\ell)} + \dots0, and stability is established by parameterizing Hlogical=iJiσz(i)+i<jJijσz(i)σz(j)+i<j<Jijσz(i)σz(j)σz()+H_{\rm logical} = \sum_{i}J_i\,\sigma_z^{(i)} + \sum_{i<j}J_{ij}\,\sigma_z^{(i)}\sigma_z^{(j)} + \sum_{i<j<\ell}J_{ij\ell}\,\sigma_z^{(i)}\sigma_z^{(j)}\sigma_z^{(\ell)} + \dots1 as a discretized negative diagonal: Hlogical=iJiσz(i)+i<jJijσz(i)σz(j)+i<j<Jijσz(i)σz(j)σz()+H_{\rm logical} = \sum_{i}J_i\,\sigma_z^{(i)} + \sum_{i<j}J_{ij}\,\sigma_z^{(i)}\sigma_z^{(j)} + \sum_{i<j<\ell}J_{ij\ell}\,\sigma_z^{(i)}\sigma_z^{(j)}\sigma_z^{(\ell)} + \dots2, where Hlogical=iJiσz(i)+i<jJijσz(i)σz(j)+i<j<Jijσz(i)σz(j)σz()+H_{\rm logical} = \sum_{i}J_i\,\sigma_z^{(i)} + \sum_{i<j}J_{ij}\,\sigma_z^{(i)}\sigma_z^{(j)} + \sum_{i<j<\ell}J_{ij\ell}\,\sigma_z^{(i)}\sigma_z^{(j)}\sigma_z^{(\ell)} + \dots3 is learned. All eigenvalues of Hlogical=iJiσz(i)+i<jJijσz(i)σz(j)+i<j<Jijσz(i)σz(j)σz()+H_{\rm logical} = \sum_{i}J_i\,\sigma_z^{(i)} + \sum_{i<j}J_{ij}\,\sigma_z^{(i)}\sigma_z^{(j)} + \sum_{i<j<\ell}J_{ij\ell}\,\sigma_z^{(i)}\sigma_z^{(j)}\sigma_z^{(\ell)} + \dots4 hence lie within the unit circle, preventing residual explosion.

Training uses Poisson-sampled loop depths per sequence and truncated backpropagation. Effective scaling laws emerge: at fixed parameter count Hlogical=iJiσz(i)+i<jJijσz(i)σz(j)+i<j<Jijσz(i)σz(j)σz()+H_{\rm logical} = \sum_{i}J_i\,\sigma_z^{(i)} + \sum_{i<j}J_{ij}\,\sigma_z^{(i)}\sigma_z^{(j)} + \sum_{i<j<\ell}J_{ij\ell}\,\sigma_z^{(i)}\sigma_z^{(j)}\sigma_z^{(\ell)} + \dots5 and increasing training FLOPs Hlogical=iJiσz(i)+i<jJijσz(i)σz(j)+i<j<Jijσz(i)σz(j)σz()+H_{\rm logical} = \sum_{i}J_i\,\sigma_z^{(i)} + \sum_{i<j}J_{ij}\,\sigma_z^{(i)}\sigma_z^{(j)} + \sum_{i<j<\ell}J_{ij\ell}\,\sigma_z^{(i)}\sigma_z^{(j)}\sigma_z^{(\ell)} + \dots6 (via loop depth Hlogical=iJiσz(i)+i<jJijσz(i)σz(j)+i<j<Jijσz(i)σz(j)σz()+H_{\rm logical} = \sum_{i}J_i\,\sigma_z^{(i)} + \sum_{i<j}J_{ij}\,\sigma_z^{(i)}\sigma_z^{(j)} + \sum_{i<j<\ell}J_{ij\ell}\,\sigma_z^{(i)}\sigma_z^{(j)}\sigma_z^{(\ell)} + \dots7 and data Hlogical=iJiσz(i)+i<jJijσz(i)σz(j)+i<j<Jijσz(i)σz(j)σz()+H_{\rm logical} = \sum_{i}J_i\,\sigma_z^{(i)} + \sum_{i<j}J_{ij}\,\sigma_z^{(i)}\sigma_z^{(j)} + \sum_{i<j<\ell}J_{ij\ell}\,\sigma_z^{(i)}\sigma_z^{(j)}\sigma_z^{(\ell)} + \dots8),

Hlogical=iJiσz(i)+i<jJijσz(i)σz(j)+i<j<Jijσz(i)σz(j)σz()+H_{\rm logical} = \sum_{i}J_i\,\sigma_z^{(i)} + \sum_{i<j}J_{ij}\,\sigma_z^{(i)}\sigma_z^{(j)} + \sum_{i<j<\ell}J_{ij\ell}\,\sigma_z^{(i)}\sigma_z^{(j)}\sigma_z^{(\ell)} + \dots9

with MNM-N0 the “unrolled” parameter count, and optimal depth and data allocations scaling as MNM-N1, MNM-N2. At test time, the performance saturates exponentially in loop steps: MNM-N3, where decay parameters scale inversely with MNM-N4.

Empirically, Parcae achieves MNM-N5–MNM-N6 lower perplexity over strong Transformer baselines at parameter counts from MNM-N7M to MNM-N8B, and matches up to MNM-N9 of the quality gain of a Transformer of double the size on CORE benchmarks. The architecture’s key contribution is the strict stability enabled by the negative-diagonal parameterization, unlocking robust, looped training and reliable scaling laws (Prairie et al., 14 Apr 2026).

4. Algorithmic Methods and Optimization Strategies

Each instantiation of Parcae Architecture introduces distinct optimization algorithms suited to its problem context:

  • In the plaquette-based parity mapping, Gaussian elimination identifies independent constraint cycles, which are compiled into local plaquettes layer by layer with explicit ancilla minimization strategies. Heuristics such as greedy or beam search are employed for compact implementations and minimal overhead.
  • For liveput-optimized DNN training, dynamic programming is used to optimize the sequence of parallelization strategies, trading immediate throughput for preemption robustness, with complexity MM0 over all feasible configurations. Lightweight migration between pipeline topologies further reduces recovery costs.
  • In looped LLMs, nonlinear dynamical system analysis leads to theoretically guaranteed spectral stability, and scaling laws are analytically derived via power-law and saturating exponential fits to empirical loss and quality metrics.

Common among all variants is the focus on deterministic, constructive, or forecast-driven compilation and adaptation, ensuring both theoretical guarantees and strong empirical results.

5. Practical Implications and Applications

Parcae architectures are distinguished by their practical ability to map complex or unstable logical problems into systematically optimized physical or computational realizations:

  • In quantum optimization, the parity-in-plaquettes scheme enables full parallelizability and constant-depth local enforcement of complex parity constraints. This allows implementation of higher-order spin-glass models and flexible side-constraint enforcement within strictly local, rectangular lattices, advantageous for both digital and adiabatic architectures.
  • In distributed DNN training, liveput optimization enables effective usage of low-cost, preemptible resources, reducing training time and cost even under highly volatile availability, a scenario common in modern cloud GPU clusters.
  • Looped LLMs with negative-diagonal stability can scale quality with compute while holding parameter count constant, yielding robust training at high depths and near-predictable improvement trajectories, offering alternatives to parameter scaling.

These properties address bottlenecks in scalability, locality, and non-stationarity across hardware, algorithm, and training domains.

6. Comparative Tables for Parcae Instantiations

Context Core Principle Primary Benefit
Parity Plaquettes Layered local constraint comp. Constant-depth, local, parallel impl.
Liveput DNN Train Forecast-based config & metric Robust, cost-efficient training
Looped LLMs Strict diagonal stability Predictable scaling, low residuals

In all contexts, the Parcae framework is characterized by rigorous algorithmic definition, explicit optimization strategies, and empirical validation demonstrating clear performance improvements relative to established baselines (Hoeven et al., 2023, Duan et al., 2024, Prairie et al., 14 Apr 2026).

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