OSA-HCIM: Saliency-Aware Hybrid CIM Framework

• OSA-HCIM is an SRAM-based computing-in-memory architecture that dynamically configures MAC precision based on saliency evaluation to enhance the energy-accuracy trade-off.
• It integrates simultaneous digital and analog CIM execution using split-port 6T SRAM cells and fine-grained precision adaptation tailored to each input.
• Its software-hardware co-design achieves up to a 1.95× energy efficiency gain and doubles throughput while maintaining minimal accuracy loss.

OSA-HCIM denotes the On-the-fly Saliency-Aware Hybrid CIM framework, an SRAM-based computing-in-memory architecture for deep neural network inference that combines dynamic, input-dependent precision configuration with simultaneous digital-domain CIM (DCIM) and analog-domain CIM (ACIM) execution. Its central objective is to allocate computational precision according to the saliency of each input, so that salient inputs are handled with higher digital precision and non-salient inputs are processed with lower-precision analog computation or discarded. In the reported 65nm CMOS implementation, OSA-HCIM is presented as the first CIM design to incorporate a dynamic digital-to-analog boundary, with the stated goal of improving the energy-accuracy trade-off relative to fixed-partition CIM designs (Chen et al., 2023).

1. Conceptual basis and design rationale

OSA-HCIM is situated within the broader CIM literature as a response to two limitations identified for prior CIM systems: the lack of flexibility in precision allocation and the associated unnecessary expenditure of computational resources on less critical operations, together with a diminished Signal-to-Noise Ratio (SNR) when more complex tasks require higher-fidelity computation (Chen et al., 2023). The framework addresses these issues by integrating CIM with Saliency-Aware Computing, defined here as a paradigm that dynamically tailors computing precision based on the importance of each input.

The architecture is organized around three named components. The first is the On-the-fly Saliency-Aware (OSA) precision configuration scheme, which dynamically sets the precision of each MAC operation based on saliency. The second is the Hybrid CIM Array (HCIMA), which enables simultaneous operation of DCIM and ACIM via split-port 6T SRAM. The third is the integrated OSA-HCIM framework itself, which combines OSA and HCIMA to fulfill diverse accuracy and power demands (Chen et al., 2023).

A central distinction from earlier hybrid CIM approaches is that OSA-HCIM does not use a fixed digital/analog partition. Instead, it performs fine-grained, multi-level precision adaptation on a per-input and per-operation basis. This suggests that the framework should be understood less as a single operating point and more as a configurable inference substrate in which saliency determines how the bit-level workload is distributed across digital, analog, and discarded computation.

2. On-the-fly saliency-aware precision configuration

The OSA scheme dynamically sets the digital-to-analog processing ratio in multi-bit MAC operations. For multi-bit activations and weights, the MAC is decomposed into bit-level operations as

$$\mathit{MAC}(\vec{A}, \vec{W})=\sum_{i=0}^{a-1}\sum_{j=0}^{w-1} 2^{i+j} \cdot \mathit{MAC}(\vec{A[i]}, \vec{W[j]})$$

where an $a$-bit input activation vector $\vec{A}$ and a $w$-bit weight vector $\vec{W}$ are represented as a sum of $a \times w$ 1-bit MACs (Chen et al., 2023).

Saliency is evaluated on-the-fly. The system first computes a subset of the highest-output-order 1-bit MACs using DCIM and quantizes their output. A hardware saliency evaluator (OSE) then estimates saliency from this partial result and uses a pre-trained mapping to determine the digital-to-analog boundary $B_{D/A}$. After that assignment, the 1-bit MACs are partitioned according to bit significance:

• $k \geq B_{D/A}$: digital-mode, using DCIM and the highest SNR
• $B_{D/A}-4 \leq k < B_{D/A}$: analog-mode, using ACIM and lower SNR
• $k < B_{D/A}-4$: discarded, on the basis of minimal impact on output (Chen et al., 2023)

The saliency score is defined as the accumulation of quantized highest-order digital MAC results:

$a$0

The boundary is then selected from pre-trained thresholds $a$1 and candidate boundaries $a$2 according to

$a$3

where the threshold values are trained to satisfy a user-specified accuracy loss tolerance $a$4 (Chen et al., 2023).

This mechanism differs from Precision Gating (PG) and DRQ, which are described as allowing only two-level precision and lacking fine hardware control. OSA-HCIM instead supports multiple precision levels selected during inference. A plausible implication is that the framework converts saliency from a descriptive property of the input into a direct scheduling signal for bit-level mixed-signal execution.

3. Hybrid CIM array and circuit organization

The HCIMA is the hardware substrate that makes dynamic precision assignment executable. Its defining circuit primitive is the split-port 6T SRAM cell, which supports independent digital and analog readout from the same stored weights through separate digital wordlines (DWL) and analog wordlines (AWL) (Chen et al., 2023).

In the digital domain, HCIMA uses bit-serial input and performs digital bitwise multiplication through logic gates. Accumulation is handled by a Digital Adder Tree (DAT), providing accurate, high-SNR accumulation for saliency-critical MACs. In the analog domain, the same array supports bit-parallel analog input through DACs with flexible bit precision from 1 to 4 bits. Multiplication is implemented via charge sharing, and the output is digitized using a 3-bit SAR ADC, which is explicitly chosen to reduce area and power relative to high-resolution ADCs (Chen et al., 2023).

A key architectural property is concurrent execution: DCIM and ACIM can operate simultaneously within the same array. The paper attributes to this mode a doubling of throughput relative to single-mode CIMs. The design therefore combines two different accumulation styles—bit-serial digital accumulation and bit-parallel analog accumulation—under a common saliency-driven controller.

The reported macro organization is 64 rows × 144 columns (64b × 144b), divided into 8 Hybrid MAC Units (HMU). The peripheral circuitry includes the OSE, accumulator, digital and analog wordline drivers, digital and analog input drivers and DACs, read/write I/O, and controller. The layout results are described as showing feasible density and energy for edge-scale on-chip integration (Chen et al., 2023).

4. Software-hardware co-design and runtime control

OSA-HCIM is explicitly formulated as a software-hardware co-design. Saliency-to-boundary mapping is not hard-coded; instead, thresholds are pre-trained using a threshold selection algorithm that takes a candidate boundary list $a$5 and loss constraints $a$6 and searches for thresholds $a$7 through iterative simulation or exploration (Chen et al., 2023). This training stage defines the runtime policy by which partial digital results are converted into D/A partition decisions.

At runtime, the near-memory OSE receives quantized high-order digital MAC results, accumulates them across cycles, and assigns a D/A partition for subsequent computation. Because only a few bits of quantized saliency are processed per MAC, the OSE is reported to incur only about 1% area/power overhead (Chen et al., 2023).

Once the boundary is selected, the workload is allocated across the two execution domains. Digital MACs are sent to DCIM and scheduled serially; analog MACs with shared weights are processed in parallel through ACIM; discarded MACs are skipped. Since the digital and analog paths have different latencies and capacities, the design allows DCIM clock frequency scaling to balance workloads, with the observation that the DAT is faster than the ADC (Chen et al., 2023).

This runtime organization gives OSA-HCIM a layered control structure: high-order digital computation estimates saliency, saliency determines the digital/analog boundary, and that boundary governs the bitwise schedule of the remaining computation. The resulting precision control is therefore both input-aware and operation-aware, rather than being fixed at design time or layer granularity.

5. Reported performance and evaluation

The reported evaluations use CIFAR100 with ResNet18, with additional results for ImageNet. On these benchmarks, OSA-HCIM is described as maintaining accuracy within 0.1 to 4.8% drop from the software baseline, with the specific example 72.1% vs. 72.22% baseline given for CIFAR100. Relative to conventional DCIM, it achieves a 1.95× improvement in energy efficiency while maintaining minimal accuracy loss (Chen et al., 2023).

For the 65nm, 0.6V implementation, the reported energy efficiency on CIFAR100 is 5.33–5.79 TOPS/W. The framework is also characterized in terms of an accuracy-efficiency Pareto: operation can be tuned from a high-accuracy/medium-efficiency regime closer to DCIM to a moderate-accuracy/high-efficiency regime closer to ACIM. The paper further states that OSA-HCIM matches or beats prior work in energy efficiency when normalized for process and bit-precisions, while providing substantially greater flexibility in accuracy versus efficiency (Chen et al., 2023).

The following table summarizes the main reported implementation and evaluation figures.

Category	Reported value	Context
Process	65nm CMOS	Hardware implementation
Macro size	64 rows × 144 columns	Further divided into 8 HMU
OSE overhead	~1%	Area/power overhead
ADC	3-bit SAR ADC	Analog-domain output conversion
Energy-efficiency gain	1.95×	Relative to conventional DCIM
Throughput characteristic	Double throughput	Via concurrent digital and analog operation
CIFAR100 efficiency	5.33–5.79 TOPS/W	65nm, 0.6V
Accuracy drop	0.1 to 4.8%	Relative to software baseline

The visual analysis reported in the work further states that saliency maps assign high precision to object pixels, such as a horse’s shape, and low precision to background. This is presented as evidence that the OSE tracks task-relevant structure in a manner aligned with learned DNN saliency (Chen et al., 2023).

6. Significance, boundaries, and relation to adjacent work

The significance attributed to OSA-HCIM lies in its combination of three properties within a single CIM system: real-time saliency evaluation, dynamic digital-to-analog boundary assignment, and simultaneous digital and analog execution. Within the paper’s framing, these properties distinguish it from standard DCIM, ACIM, and prior hybrid designs that use fixed D/A partitioning (Chen et al., 2023).

Several limitations or boundaries are implicit in the reported formulation. The dynamic boundary depends on a pre-trained saliency-to-boundary mapping, so the operating trade-off is contingent on the threshold training process and the chosen loss tolerance $a$8. Likewise, the analog domain uses a 3-bit SAR ADC and supports 1- to 4-bit DAC precision, which indicates that efficiency gains are obtained partly through deliberately constrained analog precision rather than through universally high-fidelity analog accumulation. This suggests that OSA-HCIM is best interpreted as a tunable mixed-signal architecture designed to exploit non-uniform input importance, rather than as a replacement for full-precision digital execution in all operating regimes.

A common misconception would be to treat OSA-HCIM as merely a hybrid CIM macro with a static split between digital and analog sub-computation. The reported contribution is narrower and more specific: the digital/analog boundary is not fixed, but determined on-the-fly for each operation from a saliency estimate generated by partial digital computation. In that sense, the architecture couples importance estimation and precision control at runtime, making saliency part of the computational data path rather than an offline annotation or pruning signal (Chen et al., 2023).