Optical Priority Queues

• Optical priority queues are buffering architectures that assign each packet a unique rank and ensure departures occur in strict priority order.
• The design integrates a crossbar switch, fiber delay lines, and layered FIFO multiplexers to emulate electronic queue semantics using static delay elements.
• Recent constructions achieve subexponential buffer scalability (B = 2^Θ(√M)) while maintaining collision-free routing and strict flow conservation.

Optical priority queues are buffering architectures deployed in all-optical network switching to implement strict priority-based departure and loss disciplines without resorting to electronic memory. Each packet entering such a queue is assigned a unique priority upon arrival, and departure always occurs in strict priority order. When the system buffer is full, an arriving packet may be dropped; the lowest-priority (least urgent) packet is always the one discarded. Due to the constraints of optics—specifically, that photonic memory is best realized via fixed-length fiber delay lines and non-blocking crossbar switches—architecting scalable optical priority queues has been a longstanding open problem in the field of optical networking. The major technical challenge is to emulate the strong semantics of electronic priority queues using only static delay elements and passive, high-speed switching.

1. System Architecture and Components

Fundamental to modern constructions is a feedback network comprising a single $(M+2)\times(M+2)$ all-optical crossbar switch and $M$ fiber delay lines (FDLs) (Tang et al., 2019, Tang et al., 2016). The architecture dedicates:

• One crossbar input to external packet arrivals
• One output to departures
• One output to losses (packets dropped at full buffer)
• The remaining $M$ crossbar inputs and outputs are paired to create internal FDL connections, typically with a configuration of carefully chosen delays $d_1, ..., d_M$

Critically, instead of connecting these fiber delay lines directly, high-performance architectures introduce layers of small FIFO (First-In-First-Out) multiplexers in feedback, realized themselves via secondary crossbar switches and additional short FDLs. Specifically, the network is partitioned into $2\ell-1$ (or $2m-1$, with $M = \Theta(\ell^2)$) layers or groups. Each layer contains multiple (typically three or four) 4-to-1 FIFO multiplexers, and these serve as the buffering granularity forming the backbone of the priority scheduling.

All multiplexer building blocks are constructed recursively: 4-to-1 multiplexers are realized by cascades of 2-to-1 FIFO multiplexers. Each such 2-to-1 multiplexer, in turn, can be implemented with a small crossbar plus $O(\log B_j)$ FDLs where $B_j$ is the multiplexer buffer size. All secondary switches and delay lines are logically “folded” into the main crossbar plus $M$ FDL count to ensure bounded hardware complexity.

2. Packet Tagging, Routing, and Loss Disciplines

Each buffered packet is labeled with a tag $M$0, equal to its current rank among all buffered and arriving packets (with $M$1 indicating highest priority). Tags are updated after each departure or arrival and are guaranteed to change by at most one per time slot, maintaining tag monotonicity.

The set of possible tag values is statically partitioned into contiguous intervals $M$2, one per layer. At any slot, packets whose tag falls in $M$3 are routed by the crossbar into layer $M$4, achieving tiered buffering and locality by current priority. Routing is thus self-routing: the tag uniquely determines the destination layer. Within a layer, packets are balanced across parallel 4-to-1 FIFO multiplexers using a round-robin or load-minimizing policy; up to 12 packets per layer can be accommodated without input collision due to the arrangement of 3 multiplexers × 4 inputs.

Departure and loss are implemented as follows:

• If a departure is requested, the crossbar compares any arriving packet and the head packets from the top two layers (layers 1 and 2), forwarding the highest-priority packet to the system output.
• If the buffer is full and a new packet arrives, the candidates (new and oldest packets from the bottommost layer, $M$5) are compared, and the lowest-priority among them is routed to the loss port.
• In all cases, in-layer multiplexers emit at most one packet per slot (FIFO non-idling), ensuring exact flow conservation.

3. Subexponential Buffer Scalability: $M$6

A principal advance of recent constructions is achieving subexponential buffer sizes in the number of hardware delay lines and switch ports. The crucial parameter is $M$7 (or $M$8), with the relationship $M$9.

With this setup, the total queue buffer size is given by:

$M$0

This construction exploits the layering and multiplexing approach: by grouping delay lines into layered FIFO multiplexer banks and using rank-based packet routing, the network breaks the previous polynomial barrier for optical priority queues. For context, the previously best explicit designs (sorting-based routing and recursive layering [Sarwate & Anatharam 2006; Chiu et al. 2007]) could only achieve $M$1 or $M$2 buffer sizes. The above exponential improvement remains strictly below the information-theoretic limit of $M$3, as proven upper bounds (Tang et al., 2016).

4. Correctness Guarantees and Key Lemmas

The constructions satisfy the axioms of an ideal (electronic) priority queue—flow conservation, non-idling, maximum-buffer-use dropping, highest-priority departure, and lowest-priority drop when full—by virtue of several inductively-proven invariants:

• Tag Drift Lemma: Any packet’s tag changes by at most 1 per time slot.
• Tag Range Lemma: For any layer $M$4, packets in that layer at time $M$5 have tags satisfying

$M$6

with $M$7, bounding escape from assigned intervals.

• No Collision Lemma: No more than 10 (or 13 per (Tang et al., 2016)) packets ever simultaneously target the same layer or group, ensuring round-robin (or dedicated-link) input assignment is always feasible.
• Balance Lemma: Within each trio of multiplexers in a layer, occupancy difference is at most 1, thanks to cyclic input and FIFO properties.
• No Internal Loss Lemma: No packet is ever dropped within layers; only explicit buffer-overflow drops occur at full system occupancy.
• Exact Emulation Theorem: The architecture exactly emulates the discrete-time semantic of an ideal priority queue of buffer size $M$8.

Proofs in both (Tang et al., 2019) and (Tang et al., 2016) proceed by induction on slot time, leveraging the self-routing structure and the balanced multiplexers.

5. Routing Policies and Scheduling Procedures

Each slot operates in three algorithmic phases:

1. Departure/Loss Handling:
   • A controller issues a departure command if needed. The highest-priority among eligible packets (including newly arrived and those exiting the first two layers) is selected for output.
   • On buffer-full arrival, the lowest-priority among at-risk packets is identified for loss.
2. Priority Re-Ranking:
   • Departures or losses trigger a global recalculation of packet ranks, yet adjustment is bounded to $M$9 per slot.
3. Traffic Redistribution:
   • Packets are returned to the appropriate interval group $d_1, ..., d_M$0 (or layer $d_1, ..., d_M$1), routed to the least-occupied multiplexer within the group to preserve load balancing.
   • Assignment is guaranteed collision-free due to design constraints.

Internal state variables include: for each $d_1, ..., d_M$2 and sub-queue $d_1, ..., d_M$3, buffer occupancy $d_1, ..., d_M$4. Pseudocode implementing this policy is provided directly in (Tang et al., 2016).

6. Comparison with Prior Designs

A historical survey highlights major explicit constructions:

Construction	Buffer Size	Complexity
Sarwate & Anatharam (2006)	$d_1, ..., d_M$5	Requires explicit sorting per slot, combinatorial routing
Chiu et al. (2007)	$d_1, ..., d_M$6	Recursive layering, heavy combinatorial control
Datta (2017)	$d_1, ..., d_M$7	High polynomial, large switch/FDL overheads for large $d_1, ..., d_M$8
Multiplexer-based (current)	$d_1, ..., d_M$9	Single $2\ell-1$0 switch, $2\ell-1$1 FDLs, modest multiplexer overhead

The multiplexer-based architectures uniquely combine modest implementation overhead (one crossbar, a manageable bank of FDLs, and small FIFO multiplexers) with subexponential scalability, achieved through self-routing policies and layered buffering (Tang et al., 2019, Tang et al., 2016). The complexity of per-packet control is reduced to $2\ell-1$2 or $2\ell-1$3, in contrast to the heavy combinatorial requirements of global sorting approaches.

7. Implementation and Outlook

Implementation feasibility is aligned with all-optical technologies, as the requisite switches and fiber delay lines are within reach of contemporary photonic integration. Multiplexer building blocks can be constructed recursively from compact secondary switches and a logarithmic number of FDLs per buffer size, all folded into the main architectural footprint.

A plausible implication is that, assuming sufficient photonic device miniaturization and low-loss FDLs, these architectures bridge the key gap between theoretical bounds and explicit practical constructions, making them relevant to emergent terabit-scale optical buffer designs. The step from polynomial to subexponential buffer capacity, while maintaining fixed hardware complexity, represents a substantial advance for lossless all-optical contention resolution in high-performance networks.

References: (Tang et al., 2019, Tang et al., 2016)