Multi-stage INRN: Hardware-Efficient Pipelines

• The paper demonstrates that multi-stage INRN achieves efficient hardware realization by partitioning activation functions across N-staged multiply-accumulate units, reducing area, power, and latency.
• Multi-stage INRN is defined by a pipelined architecture that sequentially computes polynomial approximations for smooth or piecewise activations, enhancing frequency coverage and reducing spectral bias.
• The approach yields significant practical improvements, including up to 97% reduction in resource usage and improved PSNR for image reconstruction, establishing its superiority over traditional INR methods.

Multi-stage INRN refers to a family of hardware-efficient Implicit Neural Representation Networks (INRs) that leverage a unified, multi-stage pipelined architecture for computing activation functions, exemplified by the QuadINR framework employing piecewise quadratic activations. This approach centers on the hardware realization and theoretical advances allowing superior expressivity and energy efficiency for INR models, particularly in image and video reconstruction domains, while radically reducing area, power, and latency demands relative to previous INR activation paradigms (Zhou et al., 20 Aug 2025).

1. Unified N-Stage Pipeline Framework

The central innovation of multi-stage INRN architectures is an $N$-stage pipelined computation of smooth or piecewise activations $\varphi$, implemented as a sequenced set of hardware stages $$S_0 \rightarrow S_1 \rightarrow \ldots \rightarrow S_{N+1}$$, each performing a fundamental multiply and/or add at a fixed clock rate (e.g., 100 MHz on FPGA, 1 GHz in 28 nm ASIC). For any target activation $\varphi$, a Taylor or piecewise polynomial expansion is apportioned across $N$ steps:

• Stage $S_0$ ("Power Term Multiplier"): Computes $p_0 = x^2$ and the linear term $\pm 2x$ in tandem (supporting piecewise formulations).
• Stage $S_1$ ("Coefficient Multiplier" or "Continued Power Term"): For even-powered activations, $p_0$ is scaled by $\varphi$0; odd-powered cases continue with $\varphi$1. For piecewise quadratic, the terms are summed at this point.
• Stages $\varphi$2 ("Multiply + Accumulate"): Each successive stage increments the polynomial approximation, multiplying by $\varphi$3, scaling by $\varphi$4 or $\varphi$5, and accumulating.
• Stage $\varphi$6 ("Final Accumulation"): Outputs the final result.

In the canonical QuadINR design, $\varphi$7 suffices, with $\varphi$8 computing $\varphi$9 and $$S_0 \rightarrow S_1 \rightarrow \ldots \rightarrow S_{N+1}$$0 in parallel, and $$S_0 \rightarrow S_1 \rightarrow \ldots \rightarrow S_{N+1}$$1 summing them. These activation modules are inserted between the multilayer perceptron (MLP) linear layers, yielding an overall composition:

$$S_0 \rightarrow S_1 \rightarrow \ldots \rightarrow S_{N+1}$$2

where $$S_0 \rightarrow S_1 \rightarrow \ldots \rightarrow S_{N+1}$$3 denotes the $$S_0 \rightarrow S_1 \rightarrow \ldots \rightarrow S_{N+1}$$4-th affine transform.

2. Piecewise Quadratic Activation and Fourier Analysis

QuadINR's activation function $$S_0 \rightarrow S_1 \rightarrow \ldots \rightarrow S_{N+1}$$5 is defined periodically ($$S_0 \rightarrow S_1 \rightarrow \ldots \rightarrow S_{N+1}$$6) on each period as:

$$S_0 \rightarrow S_1 \rightarrow \ldots \rightarrow S_{N+1}$$7

The derivative is:

$$S_0 \rightarrow S_1 \rightarrow \ldots \rightarrow S_{N+1}$$8

Periodic extension ensures smooth, rich spectral content. The closed-form Fourier expansion,

$$S_0 \rightarrow S_1 \rightarrow \ldots \rightarrow S_{N+1}$$9

provides high harmonic coverage, more effectively mitigating spectral bias in INRs than classical Taylor-truncation or unimodal activations (Zhou et al., 20 Aug 2025). The construction achieves exactness over each segment, unlike truncated Taylor series.

3. Composition of Pipeline Stages in Network Mapping

Each network layer applies the per-stage transforms $\varphi$0 such that:

$\varphi$1

Defining $\varphi$2, $\varphi$3, and $\varphi$4, the final output becomes:

$\varphi$5

This structural interleaving of affine and activation modules yields deep, expressive function classes within minimal hardware overhead.

4. Hardware Realization and Module Metrics

The unified $\varphi$6-stage pipeline is directly mapped to hardware for both FPGA and ASIC targets. For a single piecewise quadratic activation ($\varphi$7):

FPGA (Xilinx VCU128, 100 MHz):

Module	LUT	FF	DSP	LUTRAM	BRAM	Power (mW)	Latency (ns)
Single Activation	1258	97	2	0	0	28	20

Full Five-Layer INR Accelerator:

Component	LUT	FF	DSP	LUTRAM	BRAM	Power (mW)	Latency (ns)
MAC Array	244759	442268	5130	14394	0	6350	3760
AF ×4 modules	4×1258	4×97	4×2	0	0	112	80
Others/Total	250376	541726	5138	14790	231	7542	14240

ASIC (28 nm, 1 GHz, activation for 768×512 image):

Design	Area (μm²)	Static P (mW)	Dyn. P (mW)	Energy (μJ/img)
QuadINR	1914	1.54	6.14	9.69
SIREN	8415	6.83	23.30	36.79
Gaussian	37099	20.60	112.25	177.30
WIRE	74536	32.00	228.75	362.19
FINER	25765	15.34	69.45	109.60
Sinc	6582	5.12	16.55	26.10

This highlights the area, power, and runtime efficiencies accomplished by the piecewise quadratic design over previous sinusoidal (SIREN), Gaussian, wavelet, and Sinc-based AFs (Zhou et al., 20 Aug 2025).

5. Pipelined Hardware Implementation: Pseudocode Description

The hardware mapping corresponds to the following pipeline (shown for FP32 precision):

$S_0$7

Each clock cycle performs the necessary floating-point multiplications and additions, resulting in a throughput of one $\varphi$8 computation per cycle for minimal pipeline depth.

6. Comparative Efficacy and Impact

The multi-stage, piecewise quadratic INRN (QuadINR) achieves substantial quantitative advantages:

• Area (ASIC, 28 nm): $\varphi$9 vs $N$0 (SIREN), and up to $N$1 vs WIRE ($N$2)
• Dynamic Power (ASIC, 28 nm): $N$3 mW vs $N$4 mW (SIREN), and up to $N$5 vs WIRE ($N$6 mW)
• Latency (FPGA): $N$7 ns per $N$8 vs $N$9 ns (SIREN), $S_0$0 ns (WIRE)
• Resource Savings (FPGA): Activation modules cut to $S_0$1 LUT ($S_0$2 to $S_0$3 vs SIREN/WIRE) and $S_0$4 mW per instance ($S_0$5 power); end-to-end accelerator area and power are similarly reduced.
• Signal Reconstruction Performance: Up to $S_0$6 dB PSNR improvement on Kodak images over prior INR approaches (QuadINR vs FINER).

These results establish the unified N-stage pipeline with piecewise quadratic activation as the most hardware-efficient documented INR framework, achieving high-frequency representational fidelity and minimal power, area, and delay overhead (Zhou et al., 20 Aug 2025).