Memory Induction Unit (MIU)
- Memory Induction Unit (MIU) is a meminductor whose inductance varies with integrated charge, providing circuits with memory of past currents.
- It harnesses ferromagnetic core dynamics and LLG-based modeling to produce hysteresis and adaptive resonant frequency in RLC networks.
- MIUs offer innovative pathways for neuromorphic architectures and deep learning, while presenting challenges in scalability and precise circuit modeling.
A Memory Induction Unit (MIU) is a two-terminal circuit element whose inductance is a function of the integrated charge , endowing it with memory of past currents via the magnetic state of its core. The MIU is realized by a coil wound on a ferromagnetic core, where the time-dependent magnetization imbues with nontrivial dynamics. Acting as a meminductor—a complement to the memristor (memory-resistance) and memcapacitor (memory-capacitance)—the MIU enables forms of adaptive temporal processing unattainable in conventional resistor- or capacitor-based memory elements. The MIU’s inductive memory can be applied for neuromorphic computing, deep learning, and biomimetic circuit architectures by leveraging both its charge-dependent time constants and energy storage mechanisms (Wang, 10 Dec 2025).
1. Definition and Constitutive Relationships
The MIU is defined by an inductance that is not fixed but evolves according to the time integral of current:
- Flux–charge relationship:
- Voltage–current law:
The origin of this memory is the Landau–Lifshitz–Gilbert (LLG) dynamics dictating the evolution of magnetization under the influence of the driving current. Given , the paper derives the dependence from a potential–charge relation as . Simulated and experimental data indicate that typically changes in a staircase fashion with respect to accumulated charge.
2. MIU-Based Circuit Modeling
The canonical context for studying an MIU is the series R–L(q)–C circuit. The system obeys:
- Kirchhoff’s voltage law:
- State-space form (with , , ):
\begin{align*} \dot{x}_1 &= x_2 \ \dot{x}_2 &= \frac{1}{L(x_1)} \left[ -R x_2 - \frac{dL}{dx_1} x_22 - x_3 \right] \ \dot{x}_3 &= \frac{x_2}{C} \end{align*}
The time-dependent resonant frequency and damping constants become functions of :
3. Dynamic Memory Effects and Hysteresis
The memory encapsulated in the MIU results in hysteresis effects and adaptive filtering:
- Hysteretic response: The flux–charge (–) and inductance–charge () curves exhibit hysteresis stemming from the rotational LLG model, with .
- Adaptive frequency: As varies, shifts, modifying the band-pass properties of the RLC circuit in real time.
- Time-domain response: The step response is generalizable to:
Thus, both damping and oscillation frequency are modulated by the MIU’s memory, yielding adaptive and hysteretic band-pass behavior not seen in conventional RLC networks.
4. Experimental Realizations and Bio-Inspired Demonstrations
Experimental MIUs have been constructed from coils wound on high- ferromagnetic cores, with digital emulation circuits measuring current and updating stepwise (e.g., a decrease in per stimulus pulse). The discrete nature of stepwise change is evidenced in measured data.
A notable application is the amoeba-mimicking experiment: when a sequence of temperature-drop pulses is imposed as , the MIU adapts its after each event, shifting accordingly. This produces "spontaneous in-phase slowdown" at later intervals even in the absence of input, thereby reproducing primordial learning, timing, and anticipation behaviors observed in biological amoebae. The MIU thus encodes not just memorization but interval timing and predictive anticipation (Wang, 10 Dec 2025).
5. Architectures for Neuromorphic and Deep Learning Circuits
The MIU enables neuromorphic circuit architectures beyond memristor-only paradigms:
- Single MIU unit: Input layer (analog ) drives a hidden MIU–C stage responsible for adaptive resonance/energy storage. Output is a damped oscillation governed by .
- Multi-layer decomposition: Layers separately implement decay and oscillation, composable into more complex waveform approximators.
- Functional advantages: MIUs confer tunable resonant/band-pass filtering via , leverage both magnetic and electric energy domains, and naturally adapt circuit dynamics for temporal pattern learning. Such features are unattainable with resistance-based memories alone.
Prospective hardware includes MIU arrays in crossbar networks, integration with memristive synapses, and on-chip ferromagnetic MIUs for spiking neural circuits.
6. Physical Limitations and Open Research Challenges
Several constraints and gaps remain:
- Core limitations: Finite magnetization, saturation, hysteresis, and eddy-current losses restrict performance; these are omitted in idealized MIU models.
- Scalability: On-chip inductors exhibit low relative permeability, significant area overhead, and limited tunable range, posing barriers for VLSI integration.
- Operational speed: LLG-driven core magnetization operates at nanosecond to microsecond scales—slower than standard CMOS switches—impacting circuit response latency.
- Modeling fidelity: Real-world magnetic cores are multi-domain and nonuniform, yet current models often assume idealized single-domain rotation.
- Design tools: There is a lack of mature SPICE models and circuit synthesis frameworks specialized for meminductors.
Another open direction is the systematic integration of MIUs alongside memristors and memcapacitors for creating universal second-order computing primitives.
7. Key Equations and Circuit Schematic Summary
| Relationship | Equation / Description | Context |
|---|---|---|
| Flux–charge | Fundamental constitutive law | |
| Voltage–current | MIU terminal behavior | |
| State evolution | RLC with MIU | |
| Resonant frequency | Adaptive filtering | |
| Damping time | Energy dissipation |
- Basic MIU structure: Coil + magnetic core
- Circuit integration: MIU in series R–L(q)–C networks, layered blocks for and
These relationships underpin the theoretical, experimental, and practical exploitation of the MIU as a fundamental building block in neuromorphic circuits (Wang, 10 Dec 2025).