Memory as a Gate (MAG)

Updated 18 August 2025

Memory as a Gate (MAG) is a paradigm where memory devices perform active logic operations, merging storage with computational functionalities.
It leverages innovative materials and architectures, from memcapacitive systems to quantum memories, achieving reprogrammable and multifunctional logic.
MAG reduces the von Neumann bottleneck and energy dissipation, enabling adaptive, brain-inspired computing in integrated systems.

Memory as a Gate (MAG) denotes a paradigm in which memory elements are not passive storage units but actively participate in computational gate operations. In this framework, the same hardware or system that encodes the logic state can, through external control or signal modulation, perform logic functions, enabling the direct fusion of computing and memory. This concept spans several domains, including memcomputing with memcapacitive and memtranstor devices, gate-tunable anisotropic resistors, cavity magnonic tristability, gate-programmable ferroelectric memories, memristor-aided logic design, adaptive neural gating, and advanced quantum and topological architectures.

1. Physical Principles and Device Architectures

MAG implementations leverage devices whose internal state, altered by historical inputs, affects their future response. In membrane memcapacitive systems (Pershin et al., 2014), the capacitance is determined by a flexible membrane subject to a double-well potential. Binary logic states are encoded by the membrane’s position $y$ , evolving under:

$\begin{align*} q(t) &= C(y) V_C(t) \ \frac{dy}{d\tau} &= \dot{y} \ \frac{d\dot{y}}{d\tau} &= -4\pi^2 y\left[\left(\frac{y}{y_0}\right)^2 - 1\right] - \Gamma\dot{y} - \left(\frac{\beta(\tau)}{1+y}\right)^2 \end{align*}$

In memtranstor devices (Shen et al., 2016), memory and logic are unified by nonlinear magnetoelectric coupling in Ni/PMN-PT/Ni heterostructures. The output state (read as magnetoelectric voltage $C_E$ ) is set by sequential voltage pulses $X_1$ , $X_2$ that reversibly control ferroelectric polarization. The crucial relation is:

$C_E = \frac{dE}{dH}$

Gate-tunable devices, such as ultra-thin GaTe (Wang et al., 2019), utilize band structure anisotropy, enabling giant anisotropic resistance (GAR) under gate modulation; the resistance ratio $I_y/I_x$ can span up to $10^3$ .

2. External Signal Modulation and Logic Realization

A defining feature of MAG is that logic operations are selectable via external control signals, without physical reconfiguration. In memcapacitive networks (Pershin et al., 2014), logic polymorphism is achieved: a fixed circuit topology can perform implication, OR, NAND, NOT, etc., by varying pulse amplitudes $\beta_1$ , $\beta_2$ . For example, material implication logic emerges when only certain amplitude combinations cause the output device to flip state.

In memtranstor elements (Shen et al., 2016), the logic gate (NOR or NAND) is determined by input pulse sequences, with device state transitions directly mapped to output logic:

$X_1$	$X_2$	$C_E$ (output)	Logic Output
0	0	High (+)	1 (NOR)
1	0	Low (+)/–	0 (NOR/NAND)
0	1	Low (+)/–	0 (NOR/NAND)
1	1	Negative	0 (NAND)

In magnonic tristable cavities (Shen et al., 2021), drive power levels select among multiple stable frequency shifts, with each mapped to ternary logic states (0, 1, 2).

3. Polymorphism, Multifunctionality, and Brain-Inspired Computation

MAG architectures are inherently polymorphic: the same circuit or device performs vastly different logic functions under different external controls. This mirrors brain-like computation, where circuit function is modulated by signal timing and amplitude, rather than rewiring. Memcapacitive polymorphism (Pershin et al., 2014) enables massive parallelism and flexible logical assignment, analogous to neural circuit reuse.

The GATE model (Liu et al., 22 Jan 2025) formalizes this with a multi-lamellar hippocampal-inspired architecture, employing gating mechanisms (CA3 region, persistent EC3 activity) to control working memory and selective readout. Population-level gating equations, e.g.,

$\frac{dr}{dt} = (1 - r) p_{01}(I) - r p_{10}(I)$

describe the persistency and gating of memory at a neuronal population scale.

4. Advanced Materials and Device Engineering

Material choice is pivotal for MAG: graphene membranes (Pershin et al., 2014) provide mechanical bistability and nanometer scalability; PMN-PT ferroelectric substrates (Shen et al., 2016) offer stable polarization; 2D semiconductors like GaTe (Wang et al., 2019) support large, gate-modulated anisotropy; CuInP $_2$ S $_6$ /MoS $_2$ /graphite stacks (Li et al., 2022) enable vertical gate-programmable ferroelectric memories with on/off ratios exceeding $10^5$ .

Gate-controlled architectures (e.g., vdW floating-gate GaTe memory (Wang et al., 2019), gate-programmable ferroelectric memories (Li et al., 2022)) facilitate multifunctional, direction-sensitive, and analog memory. In such systems, external gate voltages tune carrier density and modulate memristive switching, often supporting multilevel conductance (essential for neuromorphic applications).

5. Quantum and Topological Gate-Memory Integration

MAG extends to quantum memory, as in cascaded random-access quantum memory (Li et al., 18 Mar 2025). Quantum information is stored in high-coherence cavity modes, accessed via buffer-transmon swaps (beamsplitter Hamiltonian: $H_{bs}(t) = \sum_i [g_i(t)/2] (a_B^\dagger a_{S_i} + a_B a_{S_i}^\dagger)$ ) and subjected to universal gates. Per-mode error rates ( $<1.5\%$ ) are below surface code thresholds, supporting fault-tolerant quantum operation.

Majorana edge mode quantum memory (Bedow et al., 13 May 2025) harnesses topological protection: MEMs store the qubit; operations (Z-/X-/Hadamard) are performed by braiding vortex-bound Majorana zero modes, with gate fidelity ensured by geometric phase accumulation,

$\Delta \phi = \arg\langle m(t_0)|m(t)\rangle - \mathrm{Im}\int_{t_0}^{t}\langle m(t')|\dot{m}(t')\rangle\,dt'$

6. Application Domains and System-Level Implications

MAG principles underpin logic-in-memory architectures (MAGIC (Bende et al., 2023)), where memristive devices store and transform digital logic states within the same array. Reliable logic operation is achieved by tuning SET-to-RESET voltage thresholds, demonstrated for OR and NOT gates; energy consumption is dominated by initialization (up to 85% of total), with execution and readout consuming the remainder.

MAG enables integrated logic-memory devices, reducing von Neumann bottlenecks and energy dissipation. Gate-programmable ferroelectric devices (Li et al., 2022) offer analog programmability and multilevel synaptic weights, vital for neuromorphic engineering.

7. Future Perspectives and Limitations

MAG approaches favor nonvolatile, reconfigurable, and analog computation, with polymorphic logic facilitating real-time adaptation and multifunctionality. Key challenges lie in material stability, precise interface control, and integration of heterogeneous devices. Quantum and topological MAG implementations must address coherence, cross-talk, and scalable error correction. Continued advances in material science, circuit engineering, and computational neuroscience will shape the evolution of MAG architectures toward high-density, low-power, adaptive computing.

MAG encapsulates a broad class of architectures in which memory and computation are inseparable, reprogrammable, and governed by signal-tunable device physics. This paradigm is realized across hardware domains—including memcapacitive networks (Pershin et al., 2014), memtranstors (Shen et al., 2016), gate-tunable anisotropic devices (Wang et al., 2019), magnonic memories (Shen et al., 2021), ferroelectric gates (Li et al., 2022), memristor-aided logic arrays (Bende et al., 2023), brain-inspired gating (Liu et al., 22 Jan 2025), and fault-tolerant quantum/topological memories (Li et al., 18 Mar 2025, Bedow et al., 13 May 2025)—with polymorphism, nonvolatility, and integrated computational functionality as recurring themes.