Memory Automation

• Memory automation is a class of architectures, algorithms, and systems that dynamically manage memory allocation, migration, and usage.
• It spans hardware, OS/runtime, and application levels, integrating techniques like profiling, formal methods, and machine learning for efficiency.
• Case studies such as MobileGPT and LEGOMem demonstrate its practical impact with improved throughput, reduced latency, and energy savings.

Memory automation denotes the class of architectures, algorithms, and software systems that manage, optimize, and abstract away memory-related decisions in computing infrastructure without direct manual intervention. Modern memory automation spans a spectrum from low-level hardware mechanisms for page/data migration in heterogeneous memories, to operating system and runtime-level data placement and dynamic allocation, to application-level frameworks that synthesize, retrieve, or adapt task-oriented procedural “memories” for complex workflow execution. Core to memory automation is the use of monitoring, learned policies, formal logic, or embedded memory models to dynamically and efficiently govern allocation, migration, and usage, often in the presence of heterogeneity (e.g., NVM+DRAM), multi-agent systems, or high-level semantic tasks.

1. Automated Memory in Task and Workflow Automation

Recent advances in LLMs and multi-agent systems have prompted the emergence of LLM-driven frameworks for the automation of procedural memories to support high-level, context-aware workflow execution:

• Mobile Task Automation: Systems such as MobileGPT implement a four-stage memory-augmented task automation loop: Explore (enumerate possible sub-tasks on each app page), Select (match user goal to sub-tasks via embedding similarity), Derive (LLM-guided action synthesis), and Recall (matching current task to cached sequences of sub-tasks for rapid replay). Sub-task memories are represented as rich text signatures with embeddings and action templates indexed hierarchically (App→Page→Subtask→Action). Memory automation in this context amortizes LLM inference costs and enables fast adaptation, achieving 82.7% cold-start task accuracy and 98.75% adaptation accuracy, with large reductions in latency and cost versus LLM-only baselines (Lee et al., 2023).
• Multi-Agent Workflow Automation: LEGOMem introduces a modular procedural memory architecture for LLM teams automating office workflows. Execution trajectories are decomposed into “full-task” and “sub-task” memories, embedded and indexed for orchestrator and agent-level retrieval. Empirical studies on OfficeBench reveal that automated memory placement—particularly at the orchestrator level—enables smaller models to close the performance gap with larger ones, and that fine-grained agent memory boosts execution efficiency (Han et al., 6 Oct 2025).
• GUI/Environment-Aware Automation: Memory modules such as MobA’s task/user/app memory trees, and MapAgent’s trajectory-based page-memory databases, represent execution history with natural language and UI structure, supporting content/relational similarity retrieval for plan adaptation and action synthesis, and yielding quantifiable gains (e.g., +12% milestone-score with memory in MobA (Zhu et al., 17 Oct 2024), +10–20% success rate in MapAgent (Kong et al., 29 Jul 2025)) over no-memory baselines.

2. Operating System and Runtime-level Memory Automation

Automated memory management is foundational to server, OS, and runtime environments, especially in systems with multi-level or heterogeneous memory:

• N-Level Aging Memory Management: Automated N-level memory allocation managers generalize classic aging-based paging algorithms to arbitrary memory hierarchies (e.g., DRAM→SCM1→SCM2→HDD). Automated managers track per-page access histories, derive bitwise “age” metrics, and assign data to levels to optimize hit/miss ratios without code modification. In simulations (DeMemory), three-level automated policies sustain hit ratios ~0.9 even as working sets exceed primary memory, consistently outperforming single-level setups (Oren, 2017).
• Profiling-based Data Placement: Online runtime systems extend heap allocators and insert monitoring hooks to sample access statistics, allocate in memory “arenas” associated with call sites, and use cost models (ski-rental, knapsack) to periodically migrate hot/cold data between fast (DRAM) and slow (Optane) tiers. Automated decision engines using access profiles achieve performance approaching that of profiling-based offline allocation, but without requiring separate training runs, outperforming default Linux memory placement under capacity pressure (Olson et al., 2021).
• Full-Stack Kernel Automation: Frameworks like memos combine kernel-level monitoring, formal page-coloring-based allocation, and predictive migration engines in systems comprising DRAM+NVM. Automated decisions span cache, channel, bank, and memory type. With OS-driven automation, systems achieve up to +19% throughput, +23% QoS, 3–83% lower memory latency, and dramatic NVM lifetime extensions (40–500x) relative to unmanaged baselines (Liu et al., 2017).

3. Hardware-Accelerated and In-Memory Automation

Automation at the hardware level extends beyond simple caching, with designs that execute data placement, migration, and even in-place computation:

• Hybrid Memory Manager Units (HMMU): Hardware memory management units map a unified address space across DRAM and NVM, track per-page/block usage, and perform migration/mapping based on built-in policies (rotating counters, bloom filters, usage bitmaps). Sub-page DRAM caching is used to avoid unnecessary full-page NVM writes. Granularity and adaptivity are controlled by online access tracking and utilization. This approach reduces energy by ~39% and NVM writes by ~25% with only ~12% performance impact vs. all-DRAM systems (Wen et al., 2020).
• Hardware-automated Memory over Storage: HAMS and its advanced variants reside in the memory controller hub to manage transparent NVDIMM and low-latency flash as a unified, cache-coherent space, handling all page movement, DMA setup, and address translation in hardware. This eliminates many OS software stack overheads, providing near-linear expansion of memory capacity and ~2x throughput and ~40% lower energy compared to the best software-only hybrid designs (Zhang et al., 2021).
• Processing-in-Memory Automation: CONTRA addresses area-constrained logic mapping for MAGIC-based (RRAM) in-memory computing, automating the LUT-based decomposition, crossbar placement, and data movement (via A* search) to minimize latency within hard area budgets. It exposes the area-delay trade-off curve for automated design-space exploration, improving area-delay product (ADP) by 2.1–13.1x over prior methods (Bhattacharjee et al., 2020).

4. Automated Dynamic Memory Manager Synthesis

Memory automation in the language/runtime layer can generate context-specific allocators:

• Grammatical Evolution for DMM Optimization: Custom dynamic memory managers (DMMs) are synthesized via profiling, BNF grammar generation, and evolutionary search. The pipeline automatically discovers application-specific allocator designs—composing building blocks such as buddy systems, segregated lists, splitting/coalescing flags—optimized for observed allocation/deallocation traces. Derived memory managers deliver 62.55% faster execution and 30.62% lower memory use relative to five general-purpose allocators in diverse benchmarks (Risco-Martín et al., 7 Mar 2024).
• Rambrain User-Space Automated Paging: Libraries such as Rambrain provide user-space wrappers (managedPtr, adhereTo) for overcommitting and swapping memory, handling budget enforcement, LRU-based eviction, prefetching, asynchronous IO, and cross-thread safety transparently for scientific and high-performance code, outperforming generic OS swapping in throughput and interactivity (Imgrund et al., 2015).

5. Verification and Formal Methods for Automated Memory

Automating memory models and memory safety proofs is essential for critical and verified software:

• GERM Framework in Coq: Formal memory frameworks model physical memory as records with address-indexed fields, generate API and verification boilerplate via code-generation assistants, and support symbolic-execution–driven automation of Hoare-triple proofs through the Execution-Verification Isomorphism (EVI). This decouples memory-model lemmas from language semantics and folds entire correctness proofs into automated computation within the proof assistant (Yang et al., 2018).
• Automata-on-Memory Processors with Automated Mapping: In the context of high-throughput pattern recognition, CAMA automates the encoding, mapping, and bank allocation of NFA state-machines directly onto content-addressable memory arrays for optimized energy and area efficiency, using an automated toolchain that selects the best encoding and tile mode for any input automaton (Huang et al., 2021).

6. Theoretical and Architectural Foundations

Memory automation mechanisms build on generalizable algorithmic frameworks, hardware primitives, and formal abstractions:

• Generalized Aging and Multi-level Policy Algorithms: Automated MAMs extend two-level paging algorithms to N-level variants using bit-count metrics and per-level policies, providing a theoretical base for automated system and OS management (Oren, 2017).
• Automated Learning in Artificial Memories: At the circuit/micro-architectural level, self-modifying paths (e.g., learned enable wiring triggered by sequences of rehearsed memory accesses) allow the hardware itself to automate common control sequences, offloading work from the CPU after sufficient repetitions—a hardware metaphor for procedural memory (Burger, 2010).

7. Limitations and Current Challenges

Despite success across domains, several limitations persist:

• OS/hardware-centric approaches may require kernel modifications, custom hardware, or specialized monitoring (e.g., kernel patches for per-arena tracking (Olson et al., 2021), on-chip PTT in HMMU (Wen et al., 2020)).
• Application-level profile-driven synthesis demands representative traces, and current simulators may under-model effects such as cache or NUMA interaction (Risco-Martín et al., 7 Mar 2024).
• The transferability of automated memory layouts across heterogeneously-structured applications is not always guaranteed, and some frameworks are limited by UI metadata structure or by not supporting vision-based UI analysis (e.g., MobileGPT’s dependence on Accessibility tags (Lee et al., 2023)).
• Hardware “learning” mechanisms (e.g., memory-to-memory wiring (Burger, 2010)) are limited by the quadratic scaling and permanence of connections; supporting loops or repeated states remains open.
• Formal frameworks (e.g., GERM) automate memory proof but may not yet fully integrate multi-language, concurrent, or distributed cases (Yang et al., 2018).

Emerging directions focus on broader generalization (e.g., >2 memory levels), tighter coupling with ML-based prediction for migration decisions (Liu et al., 2017), extending automation to file-backed and network-mapped memory, and cross-node memory sharing in disaggregated or cloud environments.

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Key References:

• MobileGPT: Human-like procedural memory in LLM-based mobile automation (Lee et al., 2023)
• LEGOMem: Modular procedural memory for multi-agent LLM workflow automation (Han et al., 6 Oct 2025)
• MapAgent: Trajectory-based memory for GUI automation (Kong et al., 29 Jul 2025)
• MobA: Multifaceted memory and planning for mobile agents (Zhu et al., 17 Oct 2024)
• N-level automated paging (DeMemory) (Oren, 2017)
• Automated DRAM/NVM allocation via OS/runtime (Olson et al., 2021), kernel (Liu et al., 2017), and hardware (Wen et al., 2020)
• Custom dynamic memory manager synthesis via GE (Risco-Martín et al., 7 Mar 2024)
• User-space memory automation (Rambrain) (Imgrund et al., 2015)
• Formal memory modeling and proof automation (GERM) (Yang et al., 2018)
• Hardware-in-memory learning (Burger, 2010), PIM mapping automation (Bhattacharjee et al., 2020), automata encoding (Huang et al., 2021)
• Hardware-automated memory-over-storage (Zhang et al., 2021)