Lossless Haar Wavelet Pyramid

• Lossless Haar wavelet pyramid is a fully invertible, multilevel decomposition framework that uses integer arithmetic for exact signal reconstruction.
• It employs a multiplierless lifting scheme with shift-and-add operations to perform efficient prediction and update steps, minimizing computational resources.
• The design achieves high throughput on FPGA platforms by cascading optimized modules in a multilevel pipeline for real-time embedded signal processing.

A lossless Haar wavelet pyramid is a multilevel, fully invertible decomposition of discrete signals using integer arithmetic and a multiplierless architecture, specifically optimized for efficient implementation in parallel and reprogrammable logic. Employing the Haar wavelet in its lifting scheme variant, the architecture enables precise lossless transformation and reconstruction of signals with minimal computational resources, eliminating all multipliers and substituting them with shift-and-add logic. The core modules operate on 8-bit samples and are configured to process data in streaming fashion, achieving substantial hardware savings and real-time throughput suitable for FPGA-based applications (Kolev, 2010).

1. Multiplierless Integer Wavelet Filter–Bank Architecture

The foundation of the lossless Haar wavelet pyramid consists of forward (analysis) and inverse (reconstruction) modules designed for integer arithmetic without multipliers. Each basic processing element comprises:

• Two programmable delays $(D_m, D_n)$ for past sample buffering.
• Three registers for temporal alignment during prediction and update steps.
• A single adder or subtractor; no explicit multiplier.
• Division by 2 or 4 is implemented via right-shift operations with conditional one-bit correction to emulate integer rounding (floor).

Forward (Analysis) Module Workflow

Given 8-bit input samples $s[2n], s[2n+1], s[2n+2]$:

• Prediction:

$$p[n] \leftarrow \left\lfloor \frac{s[2n] + s[2n+2]}{2} \right\rfloor$$

$d[n] \leftarrow s[2n+1] - p[n]$

• Update:

$$u[n] \leftarrow \left\lfloor \frac{d[n] + d[n-1]}{4} \right\rfloor$$

$s'[n] \leftarrow s[2n] + u[n]$

Output is the detail $d[n]$ and coarse-scale $s'[n]$.

Inverse (Reconstruction) Module Workflow

Given $d[n]$ and $s'[n]$:

• Undo update:

$$e[n] \leftarrow s'[n] - \left\lfloor \frac{d[n] + d[n-1]}{4} \right\rfloor$$

• Undo predict:

$s[2n] \leftarrow e[n]$

$$s[2n+1] \leftarrow d[n] + \left\lfloor \frac{s[2n] + s[2n+2]}{2} \right\rfloor$$

Output is the interleaved reconstructed samples $s[k]$.

Integer division operations use bit shifts plus single-bit conditional corrections for rounding:

$$\left\lfloor \frac{x}{2} \right\rfloor = (x \gg 1) - [x < 0 \text{ and LSB}=1]$$

$$\left\lfloor \frac{x}{4} \right\rfloor = (x \gg 2) - [x < 0 \text{ and two-bit LSB} \ge 1]$$

2. Lifting Scheme Equations for Integer Haar Wavelet

The lossless Haar wavelet lifting steps formalize decomposition and reconstruction using integer arithmetic. Let $s_{j-1}[\cdot]$ denote input at level $j-1$, $d_j[\cdot]$ the detail at level $j$, and $s_j[\cdot]$ the coarse output.

• Predict step (P):

$d_j[n] = s_{j-1}[2n+1] - s_{j-1}[2n]$

• Update step (U):

$$s_j[n] = s_{j-1}[2n] + \left\lfloor \frac{d_j[n]}{2} \right\rfloor$$

Inverse lifting undoes the forward steps:

$$s_{j-1}[2n] = s_j[n] - \left\lfloor \frac{d_j[n]}{2} \right\rfloor$$

$s_{j-1}[2n+1] = d_j[n] + s_{j-1}[2n]$

This integer lifting formulation ensures full reversibility with no loss of information due to rounding, which is essential for lossless operations.

3. Multilevel (Pyramidal) Decomposition and Reconstruction

The Haar lifting modules are cascaded to build an $L$-level wavelet pyramid. Coarse outputs at each stage serve as inputs for the next level, creating a hierarchy of resolution representations.

• Decomposition ($j-1 \to j$):

$d_j[n] = s_{j-1}[2n+1] - P(s_{j-1}[2n])$

$s_j[n] = s_{j-1}[2n] + U(d_j[n])$

• Reconstruction (reverse):

$s_{j-1}[2n] = s_j[n] - U(d_j[n])$

$s_{j-1}[2n+1] = d_j[n] + P(s_{j-1}[2n])$

After $L$ levels, one obtains the low-band $s_L$ and all detail bands $\{d_1, ..., d_L\}$, forming a fully lossless Haar wavelet pyramid. This structure is exact and supports perfect reconstruction.

4. Hardware Optimization: Multiplier Elimination and Resource Savings

The architecture completely dispenses with multipliers, replacing all fixed-point divisions by simple bit shifts plus minor corrections for sign and rounding, implemented in hardware as follows:

• Division by 2: $x \gg 1$ with conditional subtraction if $x < 0$ and least significant bit equals 1.
• Division by 4: $x \gg 2$ with subtraction if $x < 0$ and the two-bit LSB $\geq 1$.

Resource utilization in the critical path is greatly minimized:

• Per sample: 2 shifts plus 2 additions.
• Compared to floating-point implementations or 5/3 filter banks (8 multiplies/adds per sample), operational complexity is dramatically reduced.

This design is directly traceable to the modules proposed by Kolev, which serve as the blueprint for efficient reconfigurable logic wavelet processing (Kolev, 2010).

5. Implementation and Performance on Reprogrammable Logic Devices

The modules are implemented on FPGAs using standard synthesis tools:

• Devices: Virtex xc2v200e-pq240-8 (analysis), Spartan2 xc2s150-fg256-6 (reconstruction).
• Clock rate: 100 MHz.
• Resource use (forward): 30 registers, one 8-bit subtractor, one 9-bit adder.
• Resource use (inverse): 8 registers, two 8-bit adders, four 8-bit subtractors.
• Throughput: One sample per clock cycle ($100$ MSamples/s).
• Line processing: For 256 samples at 8 bits, the Haar pyramid executes in approximately $20\,\mu$s per line, while comparable floating-point DSP lifting requires $400\,\mu$s per line.

Instantiating the forward module $L$ times for decomposition and the inverse module for reconstruction yields a lossless, multilevel Haar wavelet pyramid pipeline suitable for real-time embedded or FPGA-based image and signal processing without rounding loss.

6. Context, Application, and Significance

The lossless Haar wavelet pyramid constructed with multiplierless integer lifting modules is uniquely suited to applications requiring exact reconstruction and minimal hardware cost, including real-time image processing and embedded signal analysis. The absence of multipliers directly translates to energy savings, reduced silicon area, and higher throughput, with the critical path comprising only shifts and adds.

A plausible implication is that such factorized architectures represent an efficient tradeoff between numerical fidelity and resource utilization, especially when compared with floating-point or traditional 5/3 filter approaches. Given the typical usage patterns in FPGAs and ASICs, this method enables direct integration into existing digital signal pipelines, leveraging reprogrammable logic for dynamic applications.

The approach is directly attributable to the work of Kolev and was rigorously formalized and benchmarked in (Kolev, 2010), demonstrating its technical viability and operational efficiency for lossless, integer-based wavelet decomposition and reconstruction in hardware.