ISPD19 Benchmark Suite

• ISPD19 benchmarks are a suite of 382 VLSI nets characterized by detailed pin-degree distributions, serving as a standard for evaluating RSMT algorithms.
• They employ rigorous graph construction via Hanan grids and feature encoding to test combinatorial, heuristic, and machine learning approaches in wire-length optimization.
• Empirical evaluations show methods like GAT-Steiner achieving over 99% accuracy and significant speed-ups on GPUs, highlighting scalability and practical impact.

The ISPD19 benchmarks, released as part of the ISPD19 Detailed-Routing Contest, are a widely adopted suite of nets (benchmark graphs) for evaluating rectilinear Steiner minimum tree (RSMT) algorithms in modern VLSI design contexts. Each net consists of a set of terminals and is used to assess the efficacy of heuristic, combinatorial, and machine learning approaches for Steiner-point prediction and wire-length optimization. The benchmarks provide a granular pin-degree distribution, offering nets that range from minimal to extremely large pin counts, and have become a standard for comparative analysis in RSMT research (Onal et al., 2024).

1. Benchmark Composition and Pin-Degree Distribution

The ISPD19 benchmark suite consists of 382 nets, each extracted from a contemporary VLSI design. The distribution is heavily skewed toward small nets, with most containing between 3 and 9 pins. The detailed breakdown is as follows:

Pin Degree Range	Number of Nets
3–9	335
10–19	14
20–29	3
30–39	14
40–49	3
50–99	10
≥100	≈0.02×10³

Small nets are typically solvable by simple heuristics and yield optimal solutions efficiently. In contrast, large nets (degree ≥10) are computationally intensive and represent the primary challenge for RSMT solver generalization and scalability. The benchmarks thus emphasize the necessity of robust methods for high-degree net Steiner-point placement.

2. Formal Definition: Rectilinear Steiner Minimum Tree (RSMT)

Let $P = \{p_1, \dots, p_n\} \subset \mathbb{R}^2$ denote the set of pin locations. The RSMT problem seeks a tree $T$ and Steiner point set $S$ such that $T$ spans $P \cup S$ using only axis-aligned edges. The objective function is: $\min_{T, S} \;\sum_{e \in T} \|e\|_1$ where $\|e\|_1$ denotes the Manhattan length of edge $e$. All pins (“terminals”) must be mutually connected, and any added node of degree $\geq 3$ is termed a “Steiner node.” This formalism underpins both combinatorial solvers and machine learning approaches applied in the ISPD19 context.

3. Graph Construction and Feature Encoding

The canonical preprocessing for ISPD19 nets involves forming the Hanan grid by projecting the $x$- and $y$-coordinates of all terminals, yielding a mesh of candidate Steiner nodes. The undirected graph $G = (V, E)$ for each net is constructed as follows:

• $V = P \cup H$, with $H$ denoting all empty Hanan-grid points.
• $$E = \{(u, v) \mid u, v \in V \text{ are horizontal or vertical neighbors}\}$$.

Each node $i \in V$ is encoded with a feature vector: $$\mathbf{h}_i^{(0)} = [x_i, y_i, {\bf 1}_{\{i \in P\}}]$$ where the first two components are normalized spatial coordinates and the third is a binary indicator for terminal status.

4. Evaluation Protocols and Quantitative Results

Benchmark results are typically compared against the GeoSteiner optimal wire-length. Four principal algorithms have been evaluated on ISPD19, with the following results:

Algorithm	Accuracy (% correct Steiner sets)	# Suboptimal Nets	Avg Wire-Length ↑ (%)	Max Wire-Length ↑ (%)
GAT-Steiner	99.5	2	0.29	1.84
FLUTE-3	93.7	24	0.98	6.50
FLUTE-18	95.8	16	0.57	3.40
SALT	94.9	19	0.92	5.80

Outlier analysis reveals that GAT-Steiner shows substantial improvement, registering only 70 wire-length error outliers (beyond 1.5× IQR) in contrast to FLUTE-3’s 1,322. Notably, degree-by-degree accuracy for GAT-Steiner remains above 99% even among the highest-degree nets.

5. Scalability and Impact within the VLSI Design Pipeline

The ISPD19 benchmarks have elucidated the capabilities and limitations of various RSMT methods regarding scalability, efficiency, and integration potential. For instance, the GAT-Steiner algorithm utilizes a 2-layer graph attention network that does not suffer from over-smoothing and generalizes to nets with up to 3,000 pins (testing on random nets). On modern GPUs (e.g., RTX 4090), GAT-Steiner processes thousands of nets in parallel and achieves 5×–10× speed-up over single-threaded combinatorial solvers such as GeoSteiner when batched. This suggests that the ISPD19 benchmarks, by covering diverse pin degrees and wire-length regimes, have accelerated the development of batch-processing, GPU-accelerated algorithms for VLSI routing.

6. Limitations and Generalization

Benchmark use within ISPD19 is subject to the limitations of training and evaluation protocols. For example, GAT-Steiner’s training corpus is limited to nets of degree ≤50, implying that its generalization to extremely large or highly clustered nets may incur slight performance degradation. Memory limitations also restrict batch sizes for very large nets. Nonetheless, empirical performance on ISPD19 exhibits robust generalization across net scales, with minimal observed degradation.

7. Integration and Broader Significance

ISPD19 benchmarks have proven pivotal for integrating RSMT prediction algorithms into placement and global routing flows. By providing near-optimal Steiner points in a single inference pass, algorithms tested on ISPD19 facilitate rapid wire-length estimation and topology generation, obviating the need for exhaustive combinatorial search. This practical utility underscores the benchmarks’ role as a de facto standard for VLSI algorithm comparison and as a catalyst for GPU-driven methodology adoption within the design automation community (Onal et al., 2024).