ioPUF+: I/O-Based Physical Unclonable Function

• ioPUF+ is a physical unclonable function that exploits intrinsic variations in microcontroller GPIO pull-up and pull-down resistors to generate device-unique cryptographic keys.
• It implements a novel response generation mechanism with pairwise analog voltage comparisons, BCH error correction, and SHA-256 hashing for enhanced reliability and reproducibility.
• Evaluations demonstrate high reliability (100%), balanced uniqueness (~50%), low power usage, and robust environmental tolerance, making it ideal for resource-constrained IoT and embedded systems.

ioPUF+ is a Physical Unclonable Function (PUF) implementation that leverages intrinsic process variations in the values of internal pull-up and pull-down resistors on general-purpose input/output (GPIO) pins of Commercial Off-The-Shelf (COTS) microcontrollers. The mechanism enables cost-effective secret key generation for IoT nodes and embedded systems without necessitating any new integrated circuit (IC) fabrication or dedicated custom circuitry. The ioPUF+ system encapsulates a full pipeline: it measures per-device resistor-dependent voltages, computes high-entropy response bit-strings using pairwise analog comparisons, applies BCH-based error correction, and secures privacy amplification via SHA-256 hashing — thereby producing cryptographically suitable secret keys usable for modern symmetric encryption schemes (Porlapothula et al., 23 Nov 2025).

1. Principle of Operation and Architectural Overview

The entropy source in ioPUF+ is the manufacturing-induced variability in the absolute resistance values of integrated pull-up ($R_{PU}$) and pull-down ($R_{PD}$) resistors inside each GPIO of standard microcontrollers. Each GPIO pin can selectively switch $R_{PU}$ or $R_{PD}$ into its circuit using firmware-controlled transistors ($T_{PU}$, $T_{PD}$). ioPUF+ measures these resistor values through a voltage divider configuration realized by bridging each target pin to a reference GPIO, using known external resistors and the on-chip analog multiplexer (AMUX). A 16-bit ADC with 0–5 V range digitizes the voltage developed across the divider, thus allowing indirect inference of the on-chip resistor values.

For a typical implementation on Infineon PSoC-5, 10 GPIOs are cyclically configured to yield 10 pull-up voltages ($\{V_i\}$) and 10 pull-down voltages ($\{V_j'\}$), summing to $N=20$ analog measurements per device per run.

2. Response Generation Mechanism

The ioPUF+ does not utilize a traditional challenge–response PUF protocol but instead abstracts the measurement of all $N=20$ voltages as a fixed challenge. The raw binary response is constructed from all pairwise comparisons of the measured analog voltages. For each pair $(V_{i(k)}, V_{j(k)})$, the $k$th response bit is assigned as $1$ if $V_{i(k)} < V_{j(k)}$, and $0$ otherwise. This algorithm yields a response vector of length $L = \binom{N}{2} = 190$ bits:

$$\mathbf{r} = (r_1, r_2, \dots, r_{L}), \quad r_k = \mathbf{1}\{V_{i(k)} < V_{j(k)}\}$$

This approach exploits slight but persistent chip-to-chip differences in internal resistor values, which translate into measurable and reproducible differences in voltage divider outcomes.

3. Quantitative Metrics and Experimental Evaluation

The robustness and suitability of ioPUF+ as a PUF primitive are characterized by standard metrics:

• Reliability (intra-device repeatability): Defined as $100\% - \overline{HD}_{\text{intra}}$, where $\overline{HD}_{\text{intra}}$ is the average normalized Hamming distance over repeated measurements on the same device under nominal conditions. ioPUF+ achieves 100.00% reliability (intra-HD = 0).
• Uniqueness (inter-device distinguishaibility): Mean normalized Hamming distance between responses of different devices; measured as 50.29%.
• Uniformity: Proportion of 0s and 1s in each individual device’s response vector; ioPUF+ achieves 50.54%.
• Bit-aliasing: Fraction of devices for which a specific bit position is '1'; mean value is 50.54%, indicating minimal bias.

Stability trials under stress (temperature varied up to 70 °C, supply voltage from 3.5 V to 5.25 V) show worst-case bit error rates of 2.63% and 2.10%, respectively. These values are within the correction capability of the employed error control code (Porlapothula et al., 23 Nov 2025).

4. Error Correction and Secret Key Construction

To transform noisy PUF measurements into stable cryptographic keys, ioPUF+ integrates a BCH error-correcting code with parameters $\text{BCH}(255,215,5)$: codeword length $n=255$, message length $k=215$, correcting up to $t=5$ errors (sufficient for the observed BER). The system pads each 190-bit raw response to 215 bits, computes and stores only the 40 parity bits (helper data) in nonvolatile memory. Upon regeneration, a potentially noisy raw response is padded, parity bits are appended, and BCH decoding yields the corrected reproducible PUF ID.

Privacy amplification is realized by passing the corrected 215-bit sequence to SHA-256, yielding a 256-bit digest, which serves as the ephemeral device-specific cryptographic key. The protocol follows the fuzzy extractor paradigm: stored helper data leaks negligible information, and key recovery by adversaries is infeasible without access to the live, unclonable hardware.

5. Security Applications and Demonstration

ioPUF+ supports secure key derivation protocols for device-to-device communication without persistent key storage. Demonstrated use cases include:

• Enrollment: The device and a host PC agree on a secret key $\mathbf{k}$.
• At runtime, $\mathbf{k}$ is recomputed on demand from PUF measurements.
• Application: 128-bit blocks of plaintext (e.g., ECG samples) are padded (PKCS#7), AES-128-ECB encrypted with the derived key, and transmitted; decryption is performed using the shared secret at the peer endpoint.

The system successfully encrypts and decrypts real data samples, demonstrating that the cryptographic pipeline correctly supports practical, reproducible key recovery in light of the inherent noise and environmental sensitivity of analog PUF primitives (Porlapothula et al., 23 Nov 2025).

6. Resource Consumption and Implementation Profile

ioPUF+ is engineered for microcontroller-class resource constraints. The evaluated implementation on Infineon PSoC-5 (256 KB Flash, 64 KB SRAM) demonstrates the following:

Configuration	Flash Usage	Latency	Power
PUF primitive	8.0 KB	45 ms	84.9 mW
+ BCH	15.3 KB	150 ms	80.5 mW
+ SHA-256	16.4 KB	175 ms	82.0 mW
+ AES	19.8 KB	600 ms	79.0 mW

The entire ioPUF+ pipeline, inclusive of error correction, hashing, and block cipher encryption, executes within 600 ms, maintains sub-20 KB Flash footprint, and draws <80 mW. These attributes underscore its suitability for resource-constrained IoT and embedded applications.

7. Applicability and Environmental Robustness

ioPUF+ is not vendor- or process-specific; it applies broadly to microcontrollers with programmable pull-up/down networks, an integrated ADC, and (preferably) an analog multiplexer, all of which are standard in COTS MCUs. No custom silicon design is required.

The system tolerates up to ±2.6% bit errors under combined environmental stress (±40 °C or ±1.5 V supply variance) while maintaining full key recovery due to the error correction bound of its BCH configuration. Environmental robustness enables use in diverse IoT deployments exposed to real-world variability (Porlapothula et al., 23 Nov 2025).

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ioPUF+ constitutes a reproducible, zero-silicon-overhead, I/O-based PUF methodology, providing reproducible, unbiased, and cryptographically strong keys for embedded security protocols through the exploitation of standard hardware features and robust post-processing.