Inter-Module DSP Reuse Methodology

• Inter-module DSP reuse is a design strategy that enables dynamic sharing of DSP resources through time-division and reconfiguration techniques to minimize hardware usage.
• The approach achieves substantial resource savings, such as up to 16% DSP reduction in robotics and 40–50% reduction in DSP count in HLS flows, while maintaining throughput.
• Architectural implementations like FPDA and DRACO, along with multi-pumping scheduling and subgraph caching, allow efficient arbitration and real-time resource allocation.

Inter-module DSP reuse methodology encompasses a class of design techniques that maximize the utilization of digital signal processing resources—either at the function, operator, or hardware module level—by enabling their sharing, dynamic allocation, or reconfiguration among multiple computation blocks. Modern DSP reuse approaches are motivated by the stringent area, energy, and bandwidth constraints of contemporary hardware platforms, especially FPGAs and multi-core accelerators. These techniques range from time-multiplexed resource sharing, reconfiguration-driven interconnect architectures, task-level multi-pumping, to software-level subgraph caching. While early proposals focused on hardware-level switch matrices in Field Programmable DSP Arrays (FPDAs), recent methods address dynamic runtime sharing and parallelism for deep learning, numerical simulation, and robotics acceleration.

1. Fundamental Principles of Inter-Module DSP Reuse

The primary aim of inter-module DSP reuse is to minimize the silicon area (or equivalent hardware resource consumption) allocated to DSP hardware blocks, subject to throughput, latency, and application-specific constraints. The core principle is time-division or space-division multiplexing: DSP operators or clusters are not statically bound to a single function or module but are dynamically assigned to different computation blocks as dictated by the system schedule or configuration.

This reuse may be orchestrated through:

• Programmable interconnection networks that route operands/result, making functional units available to various computation kernels (Sinha et al., 2013, Sinha et al., 2013).
• Time-shared resource groups with control logic (e.g., FSMs) ensuring mutually exclusive access among pipelined modules (Liu et al., 11 Nov 2025).
• Clock and pipeline manipulation (multi-pumping), trading increased clock rate or initiation interval for lower DSP block count (Brignone et al., 2023).
• Software-layer subgraph caching and execution pooling, amortizing operator preparation and memory over multiple invocations (Xu et al., 2022).

These approaches are tailored to different levels—hardware architecture, high-level synthesis (HLS), runtime control, or deep learning system software.

2. Architectural Instantiations and Control Mechanisms

Several architectural paradigms support inter-module DSP reuse:

• Field Programmable DSP Arrays (FPDA):
  • FPDAs employ a grid of common modules (CMs)—adders, subtractors, multipliers, scaling units, LUTs—interconnected via a programmable routing matrix. Only one function (FIR, FFT, DWT, DCT, IIR) is active at a time; switching is accomplished by loading a configuration word into the decoder, altering interconnects so the same hardware CMs are reused for different kernels (Sinha et al., 2013, Sinha et al., 2013). No fine-grained resource wastage occurs as in FPGA CLBs; all CMs contribute to the selected function.
• Multi-domain Module Sharing with Arbitration (e.g., DRACO):
  • In DRACO’s RBD accelerator for robotics, DSP groups are allocated via FSM-controlled arbitration. Modules (RNEA, Minv, ΔRNEA) share DSP block pools on a mutually exclusive basis. At each function invocation, the controller binds shared groups to the appropriate module based on non-overlapping active windows, eliminating idle cycles (Liu et al., 11 Nov 2025).
• Task-Level Multi-Pumping in HLS Flows:
  • HLS compilers can automatically bind a reduced number of DSP operators to multiple tasks by increasing pipeline initiation intervals (II), raising the target clock frequency (multi-pumping), and assigning each task to its own clock domain. Module boundaries are preserved, but task throughput is maintained while DSP count falls by ≈M× (Brignone et al., 2023).
• Dynamic DSP Subgraph Reuse in DNN Training:
  • Workload segments (“DSP-compute subgraphs”) mapped to hardware DSPs on SoCs are recognized, hashed, and cached. At run time, reuse is achieved by matching subgraphs to cached compiled instances, bypassing preparation and memory allocation overhead. This software-level mechanism enables amortized DSP setup across repeated invocations (Xu et al., 2022).

3. Scheduling, Arbitration, and Reconfiguration Algorithms

Efficient inter-module reuse depends on scheduling policies, reconfiguration algorithms, and arbitration logic.

• Reconfiguration Scheduling (FPDA):
  • At the moment of function switch (e.g., FIR→DWT), a decoder sets control lines to load the new connection matrix $M^F$, selecting the relevant set of CMs for that function; only the interconnect configuration changes, not the CMs themselves. Switching occurs on the order of tens to hundreds of ns in FPDAs, enabling microsecond-scale function re-tasking.
• Time-Shared DSP Arbitration (DRACO):
  • A small per-group FSM manages which module is currently bound to each shared DSP pool, based on the function being executed. No more than one module accesses each group per cycle, ensuring no conflicts. The minimum DSP allocation to each module is determined analytically to avoid II degradation:

  $$\text{Find minimum } D_{\text{shared}} : \text{II}_A(D_A - D_{\text{shared}}) \leq \text{II}_{\text{common}},\; \text{II}_B(D_B + D_{\text{shared}}) \leq \text{II}_{\text{common}}$$

  where $D_A, D_B$ are DSPs assigned to modules $A, B$ in isolation (Liu et al., 11 Nov 2025).

• Multi-Pumping Scheduling (HLS):

  • The HLS scheduler is instructed to assign $M$× larger initiation interval and $M$× higher frequency to each module, targeting the same throughput but with DSPs shared among $M$ tasks (Brignone et al., 2023). No change to behaviorally described (C/C++) code is necessary; resource constraints and clock domains are set via tool directives.
• Subgraph Caching and Hashing (Mandheling):
  • DSP-friendly operator groups are hashed; a global cache is checked for each subgraph before compilation and allocation. MRU eviction policy maintains the active working set within DSP-local memory constraints (Xu et al., 2022).

4. Cost Models, Throughput, and Utilization Impact

Analytical models capture the trade-offs in DSP reuse.

• FPGA/FPDA Resource Utilization:
  • In FPDAs, all CMs are used during the selected function’s execution; utilization factor can approach 100% for active operations, surpassing typical FPGA LUT utilization (~50–60%) (Sinha et al., 2013, Sinha et al., 2013).
  • Configuration overhead is amortized, since switching occurs infrequently relative to function execution time (sub-ms for reconfiguration; hours of operation per kernel in dataflow pipelines).
• Time-Shared DSP Savings (DRACO):
  • DSP reduction is quantified as $S_{\text{reuse}} = 2 \times D_\text{shared}$ per two modules, or $\sum_i D_i - \max_i D_i$ for $N$ modules with aligned activation windows. For example, in the Atlas robot, DSP usage decreased from 6,301 to 5,285 (–16.1%), and DSP utilization improved from 62% to 92% (Liu et al., 11 Nov 2025).
• Multi-Pumping (HLS):
  • DSP count after sharing is approximately $R_1 = \lceil N/(M \cdot \mathrm{II}_0) \rceil$; for $M=2$, typical savings are 40–50% in real designs (Brignone et al., 2023).
• Preparation Overhead in Subgraph Reuse:
  • Mandheling’s subgraph reuse reduces per-batch setup time by 8.5 s (from 13.02 s to 4.54 s on ResNet-34). Preparation time per batch is reduced from $N\,\bar{T}_{\text{build}}$ to $U\,\bar{T}_{\text{build}}$ for $N$ invocations and $U$ unique subgraphs (Xu et al., 2022).

5. Application Domains and Benchmarks

Inter-module DSP reuse is effective in several domains:

• Transform-intensive DSP workloads:
  • FIR, IIR, DWT, FFT, DCT, and other kernels mapped onto FPDAs or time-shared FPGA fabrics, with single digit switching times and >90% utilization (Sinha et al., 2013, Sinha et al., 2013).
• Robotics and Rigid Body Dynamics:
  • DRACO’s reuse mechanism is tailored for hardware-accelerated RBD, where module pipelines operate in non-overlapping windows, enabling up to 16% DSP reduction and utilization up to 95% (Liu et al., 11 Nov 2025).
• High-Throughput Dataflow Computation:
  • Task-level multi-pumping delivers up to 40% DSP reduction at fixed throughput and up to 50% throughput increase at fixed DSP count in HLS-generated dataflow, under 3% overhead for FIFOs and multi-clock routing (Brignone et al., 2023).
• Deep Neural Network Training and Inference:
  • Mandheling demonstrates that software-layer subgraph reuse enables 5.5× per-batch time reduction and 8.9× energy reduction in DNN training by eliminating redundant DSP operator preparation (Xu et al., 2022).
• Sequence-Parallel Transformers:
  • Dynamic sequence parallelism (DSP) in multi-dimensional transformer models allows for minimal communication and efficient reuse of communication layouts across blocks, yielding a 42–216% throughput increase and ≥75% reduction in communication volume (Zhao et al., 15 Mar 2024).

6. Constraints, Limitations, and Integration Considerations

Despite the potential, several design constraints and necessary conditions exist:

• Mutual Exclusion of Peak Demand:

DSP reuse provides savings only when modules do not simultaneously require full DSP capacity—statistically independent or phase-shifted module activation is critical. In DRACO, over-aggressive sharing that degrades module II must be avoided (Liu et al., 11 Nov 2025).

• Reconfiguration Overhead and Bounded Flexibility:

High-frequency reconfiguration is supported in FPDAs, but with overhead in routing and control. Resource sizing must anticipate the larges required module footprint.

• Static Graph and Homogeneity in Subgraph Reuse:

Subgraph hashing approaches assume static operator sequences and homogenous quantization metadata; highly dynamic graphs or mixed-precision applications require additional mechanisms (Xu et al., 2022).

• Synthesis and Timing Closure:

Multi-pumping or HLS-based sharing must respect path delays; excessive II or frequency requirements can limit attainable M factors (Brignone et al., 2023).

• Interconnect and Control Complexity:

FPDAs rely on non-blocking crossbars or switch matrices; scaling presents routing and control signal distribution challenges (Sinha et al., 2013, Sinha et al., 2013).

7. Future Directions and Generalizations

The unification of architectural, compiler, and runtime-layer DSP reuse points toward several trends:

• Adaptive, workload-aware sharing policies that dynamically track module utilization and optimize resource allocation based on real-time telemetry.
• Automatically synthesized arbitrated hardware fabrics in HLS that exploit not only intra-module but also inter-module and system-level slack.
• Integration of communication and computation reuse, such as in multi-dimensional sharding for language and vision transformers, where GPU layout switching incentives mirror DSP hardware sharing (Zhao et al., 15 Mar 2024).
• Reconfigurable compute fabrics (e.g., FPDA-like designs) with ultra-fast switching and parallelism suitable for next-generation edge, signal processing, and AI platforms.

While the detailed schedules, arbitration policies, and fabric designs must be tailored to each application’s operation profile and timing constraints, the methodology of inter-module DSP reuse offers substantial improvements in resource savings, throughput, and energy efficiency across a diverse spectrum of computation-intensive domains.