Integrator-Based Modulo ADC

• Integrator-based modulo ADC is an analog-to-digital conversion architecture that folds high-dynamic-range signals into a confined interval using continuous-time integration and reset logic.
• The design decouples effective dynamic range from the quantizer’s nominal input range, enabling significant improvements in ENOB and SINAD in high-oversampling regimes.
• Practical implementations address nonidealities with hysteresis compensation, finite slewing corrections, and low-pass filtering to ensure accurate signal reconstruction.

An integrator-based modulo ADC is an analog-to-digital conversion architecture within the unlimited sensing framework in which a continuous-time analog front end folds a high-dynamic-range input into a bounded interval, typically $[-\lambda,\lambda]$, while an internal residue state generated by an integrator and threshold-triggered reset logic preserves the information needed for digital recovery. In contrast to a conventional ADC, whose input range must exceed that of the signal to avoid clipping, a modulo or self-reset ADC applies the centered modulo map

$$\mathcal{M}_\lambda(x)=((x+\lambda)\bmod 2\lambda)-\lambda,$$

so that the observable analog waveform remains bounded even when the underlying signal amplitude is much larger. Recovery is then transferred to the digital domain, where bandlimitedness, oversampling, prediction, side information, or related structure is used to unfold the samples and reconstruct the original signal (Zhu et al., 2024, Bhandari et al., 2017).

1. Formal model and conceptual scope

Modulo sampling is also described as unlimited sampling or self-reset ADC operation. The basic premise is that dynamic-range limitations should be handled by nonlinear analog preprocessing rather than by enlarging the quantizer range. In the unlimited sensing framework, a high-dynamic-range signal $g(t)$ is decomposed as

$g(t)=z(t)+\varepsilon_g(t),$

where $z(t)\in[-\lambda,\lambda]$ is the bounded modulo signal seen by the ADC and $\varepsilon_g(t)$ is a residue that records cumulative folding in integer multiples of $2\lambda$ (Zhu et al., 2024).

What distinguishes the integrator-based variant from a purely static folding element is the mechanism by which the modulo behavior is realized. Integrator-based modulo ADCs usually integrate or accumulate the input, or an error signal, in time; whenever the internal state crosses a threshold, they perform a reset or equivalent wrap by $\pm 2\lambda$. The modulo behavior is therefore implemented by a continuous-time state machine rather than a purely memoryless nonlinearity. This makes the architecture closely related to self-reset and $\Sigma\Delta$-like loops, while remaining mathematically compatible with the same modulo map used in unlimited sampling theory (Kvich et al., 20 Jan 2025).

The core attraction of this architecture is the decoupling of effective dynamic range from the quantizer’s nominal input range. A conventional $N$-bit ADC over a full-scale range $$\mathcal{M}_\lambda(x)=((x+\lambda)\bmod 2\lambda)-\lambda,$$0 has quantization step $$\mathcal{M}_\lambda(x)=((x+\lambda)\bmod 2\lambda)-\lambda,$$1, so increasing range to accommodate large amplitudes also increases quantization noise. Modulo sensing instead maps the signal into a low-dynamic-range interval before quantization and delegates recovery of the folds to the reconstruction algorithm (Zhu et al., 2024).

2. Analog architecture and operating principle

A concrete integrator-based realization is the integrator-based modulo ADC, or I-MADC, introduced as a low-cost hardware implementation within the unlimited sensing framework. Its block structure comprises an instrumentation amplifier (IA), a pair of Schmitt triggers, an adder, an op-amp-based integrator, and a conventional ADC. The IA outputs

$$\mathcal{M}_\lambda(x)=((x+\lambda)\bmod 2\lambda)-\lambda,$$2

where $$\mathcal{M}_\lambda(x)=((x+\lambda)\bmod 2\lambda)-\lambda,$$3 is the integrator state. The Schmitt triggers compare $$\mathcal{M}_\lambda(x)=((x+\lambda)\bmod 2\lambda)-\lambda,$$4 against $$\mathcal{M}_\lambda(x)=((x+\lambda)\bmod 2\lambda)-\lambda,$$5 with hysteresis $$\mathcal{M}_\lambda(x)=((x+\lambda)\bmod 2\lambda)-\lambda,$$6, the adder forms an integrator input $$\mathcal{M}_\lambda(x)=((x+\lambda)\bmod 2\lambda)-\lambda,$$7, and the integrator evolves as

$$\mathcal{M}_\lambda(x)=((x+\lambda)\bmod 2\lambda)-\lambda,$$8

When $$\mathcal{M}_\lambda(x)=((x+\lambda)\bmod 2\lambda)-\lambda,$$9 exceeds $g(t)$0, the upper Schmitt trigger drives the integrator so that $g(t)$1 changes and forces $g(t)$2 back toward the interior of $g(t)$3; the lower branch performs the analogous action for negative overflow. When the state re-enters the hysteresis band, the trigger resets and the integrator holds its new value, thereby completing one fold (Zhu et al., 2024).

The same hardware paper introduces a gain parameter $g(t)$4, realized by the IA, with the identity

$g(t)$5

This separates the effective modulo threshold from the raw input amplitude and provides a direct analog control of dynamic-range compression. The paper defines the signal dynamic range in modulo units as

$g(t)$6

so $g(t)$7 expresses how many modulo intervals the signal span occupies (Zhu et al., 2024).

This integrator-centered architecture differs sharply from earlier modulo ADC hardware based on digital counters and DAC resets. In those systems, the modulo value is implemented as $g(t)$8, where $g(t)$9 is a finite-bit counter; dynamic range is therefore bounded by the counter and DAC resolution. The I-MADC removes the counter and DAC from the feedback loop and uses an analog integrator whose state is not bit-limited, so the design is described as having no theoretical limit on folding times (Zhu et al., 2024). By contrast, the 65 nm UDR-ADC of Krishna et al. performs sampled-amplitude modulo reduction after a sample-and-hold using a modulo circuit, quantizer, and reset logic, but it has no analog integrator in the front end; its integrator appears only as a digital cumulative sum in reconstruction (Krishna et al., 2019). The ring-oscillator architecture of Ordentlich et al. offers a different physical realization again: modulo behavior is induced in the phase domain rather than by an analog integrator state (Ordentlich et al., 2018).

3. Reconstruction principles

The reconstruction problem is to recover the unfolded sequence from bounded modulo samples. In the classical bandlimited setting, Bhandari, Krahmer, and Raskar showed that if $g(t)=z(t)+\varepsilon_g(t),$0 is bandlimited to $g(t)=z(t)+\varepsilon_g(t),$1, sampled with period $g(t)=z(t)+\varepsilon_g(t),$2, and folded by $g(t)=z(t)+\varepsilon_g(t),$3, then sufficiently high-order finite differences of the sample sequence can be made smaller than $g(t)=z(t)+\varepsilon_g(t),$4. Their sufficient condition is

$g(t)=z(t)+\varepsilon_g(t),$5

together with a difference order

$g(t)=z(t)+\varepsilon_g(t),$6

where $g(t)=z(t)+\varepsilon_g(t),$7 satisfies $g(t)=z(t)+\varepsilon_g(t),$8. Under these conditions, modulo becomes transparent to the $g(t)=z(t)+\varepsilon_g(t),$9-th difference, repeated discrete summation reconstructs the folded offsets, and the original signal is recovered up to an additive multiple of $z(t)\in[-\lambda,\lambda]$0 (Bhandari et al., 2017).

A second reconstruction line treats modulo ADCs as predictive systems. In blind modulo ADCs for vector processes, the analog front end is memoryless modulo-plus-quantizer, but the digital decoder uses a spatiotemporal predictor that the authors explicitly describe as playing the role of a digital integrator or feedback filter. The unfolded quantized signal is

$z(t)\in[-\lambda,\lambda]$1

with $z(t)\in[-\lambda,\lambda]$2, and recovery is carried out by prediction, modulo residual computation, and integer-forcing decoding. The same work also introduces automatic modulo-level adjustment through the adaptive gain $z(t)\in[-\lambda,\lambda]$3, allowing the decoder to asymptotically match unknown source statistics (Weiss et al., 2021).

Quantization-aware recovery can be strengthened with explicit fold side information. A recovery method used in practical modulo sampling with realistic ADCs employs one-bit side information indicating whether “a fold occurred since the last sample.” In that formulation the method assumes oversampling factor $z(t)\in[-\lambda,\lambda]$4 and at least $z(t)\in[-\lambda,\lambda]$5 effective bits. Integrator-based modulo ADCs naturally generate reset events or overflow flags, so this one-bit channel is structurally compatible with the hardware itself rather than an external add-on (Kvich et al., 20 Jan 2025).

4. Dynamic range, quantization, and reported performance

The principal quantitative advantage of modulo conversion is that quantization is performed over $z(t)\in[-\lambda,\lambda]$6 rather than over the full signal range. In the quantization analysis used for practical modulo sampling, the classical ADC quantization MSE scales as $z(t)\in[-\lambda,\lambda]$7, whereas modulo quantization with

$z(t)\in[-\lambda,\lambda]$8

scales as $z(t)\in[-\lambda,\lambda]$9. The paper identifies this cubic decay in oversampling factor as a key performance advantage of modulo ADCs in high-oversampling regimes, provided that the digital algorithm receives the correct modulo sample sequence (Kvich et al., 20 Jan 2025).

The integrator-based hardware paper reports corresponding experimental gains. Its abstract states that the prototype captures HDR signals with a 60-fold increase in dynamic range, achieves up to 5 Effective Number of Bits (ENOBs), and improves Signal-to-Noise and Distortion (SINAD) by 30 dB (Zhu et al., 2024). More detailed measurements include a case with $\varepsilon_g(t)$0 and $\varepsilon_g(t)$1, where conventional SINAD is 25 dB and I-MADC SINAD is 56.85 dB, a gain of $\varepsilon_g(t)$2 dB, described as equivalent to about 5 bits ENOB difference. The same paper also reports an empirical trend

$\varepsilon_g(t)$3

so each doubling of the modulo gain yields about one additional effective bit in the reported experiments (Zhu et al., 2024).

These gains are not unconditional. When no extra folding is needed, the modulo architecture may offer little or no advantage; for example, with $\varepsilon_g(t)$4, the paper reports a slight $\varepsilon_g(t)$5 dB difference between conventional and I-MADC SINAD. The significance of the architecture therefore lies in the high-dynamic-range regime, where the modulo front end prevents clipping without sacrificing fine quantization inside the bounded interval (Zhu et al., 2024).

5. Bandwidth limits, hysteresis, and other nonidealities

A central practical issue in integrator-based modulo ADCs is that modulo folding creates discontinuities and therefore very wide spectral content. Even if the input $\varepsilon_g(t)$6 is bandlimited, the folded waveform $\varepsilon_g(t)$7 is not bandlimited. Real ADCs contain track-and-hold stages that behave as low-pass filters, so a realistic converter placed directly after a modulo node effectively measures

$\varepsilon_g(t)$8

not the ideal sequence $\varepsilon_g(t)$9. Practical modulo sampling addresses this by inserting an analog mixer and low-pass filter after the modulo operation. For an ideal comb mixer

$2\lambda$0

the resulting low-pass output satisfies

$2\lambda$1

so the digital samples are mathematically identical to those of an ideal high-bandwidth modulo sampler even though the final ADC is bandwidth-limited. The paper explicitly notes that this architecture can be viewed as a front end to an integrator-based modulo core (Kvich et al., 20 Jan 2025).

Finite transition time is another nonideality. In the integrator-based hardware prototype, folds are not instantaneous because of finite slew rate in the integrator and comparators. The reported compensation method detects transition regions by sliding-window jump detection and then replaces the affected samples by linear regression based on nearby valid samples. This is a practical correction step rather than a change in the analog model (Zhu et al., 2024).

A more structural treatment of such nonidealities is provided by the theory of modulo hysteresis. The generalized operator with parameters $2\lambda$2 models hysteresis width $2\lambda$3 and finite transient duration $2\lambda$4, but the original form does not guarantee that the output remains inside the ADC range. To fix this, a modified operator $2\lambda$5 is introduced, and the paper proves

$2\lambda$6

Under the conditions

$2\lambda$7

bandlimited signals are uniquely identifiable from modulo hysteresis samples when

$2\lambda$8

and an Orthogonal Matching Pursuit or Stagewise Arithmetic OMP reconstruction can recover the folding events from Fourier-domain measurements (Beckmann et al., 8 Apr 2025). In the context of integrator-based modulo ADCs, this places hysteresis and finite reset time inside a mathematically explicit recovery model rather than treating them as unexplained implementation error.

6. Specialized signal models, multichannel extensions, and current directions

Integrator-based modulo ADCs are not restricted to classical bandlimited recovery. For finite-rate-of-innovation signals

$2\lambda$9

modulo sampling with a compactly supported kernel permits unique identification above the rate of innovation, with the number of samples for identifiability equal to the degrees of freedom. The same paper emphasizes that an integrator-based front end corresponds to a particular sampling kernel $\pm 2\lambda$0, so the FRI theory applies after specialization of the kernel and its associated Lipschitz bounds (Mulleti et al., 2022).

At the array level, modulo ADC ideas have been extended to multiple channels and massive MIMO. In blind modulo ADCs of vector processes, spatiotemporal prediction and integer-forcing decoding exploit both temporal and spatial correlation, and the decoder adapts its modulo level automatically to unknown source statistics (Weiss et al., 2021). In $\pm 2\lambda$1-MIMO, the modulo ADC is used at each RF chain, and the paper reports detection and average uplink sum-rate performances comparable to a conventional, infinite-resolution ADC when using a $\pm 2\lambda$2-$\pm 2\lambda$3 bit $\pm 2\lambda$4-ADC, together with a superior trade-off between energy efficiency and bit budget (Liu et al., 2022). These developments are not integrator implementations themselves, but they define the multichannel algorithmic environment into which integrator-based front ends can be inserted.

Recent work also focuses on robustness and lower-rate recovery. A robust blind modulo ADC proposes a reliable detector that unfolds signals without requiring the prediction error to remain bounded, thereby preventing the instability that arises when one mis-unfolded sample corrupts the adaptive predictor (Weiss, 2024). Model-based learned recovery has been proposed in the form of a deep unfolding network with a soft-quantization module that enforces the modulo prior, targeting low sampling rates and additive Gaussian noise (Kvich et al., 21 Oct 2025). A plausible implication is that future integrator-based modulo ADCs will be co-designed with recovery algorithms that explicitly model hysteresis, finite bandwidth, adaptive gain, and multichannel structure rather than assuming an ideal front end.

The present research trajectory is therefore twofold. On the hardware side, it aims at higher-speed integrators and comparators, multi-channel implementations, and closed-loop adaptive gain control. On the algorithmic side, it seeks reconstruction methods that remain stable under quantization, noise, incomplete statistical knowledge, and realistic folding transients (Zhu et al., 2024).