Hybrid Unary-Binary Architecture

• Hybrid unary-binary architecture is a computing strategy that uses unary encoding for hardware simplicity and binary representation for compact, efficient accumulation.
• It is applied in printed electronics and neural network accelerators to reduce area and power consumption while managing trade-offs in latency and accuracy.
• The design partitions computations by employing unary-based operations in the initial layers and binary arithmetic in later stages to balance robustness with performance.

Hybrid unary-binary architecture denotes a class of computational organizations in which selected signals, operands, or layers are encoded in unary form, while subsequent computation remains in compact fixed-point or positional binary form. Across the literature, this arrangement is used to preserve unary arithmetic’s hardware simplicity—such as bitwise-AND multiplication, gated accumulation, counting, or direct thermometer-code consumption—without inheriting the long bit-streams, routing expansion, and control overhead of pure-unary systems, and without paying the full multiplier and interface cost of conventional binary datapaths (Armeniakos et al., 18 Sep 2025, Vellaisamy et al., 2024, Vellaisamy et al., 2024, Zhai et al., 2020).

1. Conceptual basis and motivation

Hybrid unary-binary designs arise from a recurring hardware tension. Conventional bit-parallel binary implementations provide low latency, but they require multi-bit multipliers, adders, and multi-bit routing. Unary computing simplifies arithmetic substantially, yet it often exchanges circuit complexity for temporal length. The resulting architecture therefore places unary encoding only where it offers a decisive structural advantage, and retains binary representation where compactness and accumulation efficiency are more important.

In printed electronics (PE), the motivation is especially explicit. PE systems suffer from large feature sizes, low integration density, and tight power/area budgets. Standard binary MLP implementations require multi-bit multipliers and adders, area- and power-hungry flash ADCs followed by binary-to-unary or binary-to-thermometer encoders for sensor interfaces, and conventional digital routing of multi-bit words. Unary arithmetic offers extreme hardware simplicity: multiplication by bitwise-AND, addition by simple bit-counts or OR trees, and direct sensor-to-unary mapping if the ADC already produces a thermometer code. Its two stated drawbacks are very long bit-streams to achieve reasonable precision and the fact that serial or temporal formats incur multi-cycle operation and heavy control logic, including registers and counters (Armeniakos et al., 18 Sep 2025).

A closely related motivation appears in matrix-multiply accelerators. General Matrix Multiplication (GEMM) dominates DNN inference and training time. Traditional bit-parallel MAC engines deliver low latency at the cost of high area and power, whereas unary computing trades parallelism for time. The hybrid temporal-unary/binary formulation used in tubGEMM preserves unary simplification for one operand while keeping the other operand in conventional binary, with exact arithmetic rather than stochastic approximation (Vellaisamy et al., 2024).

In convolution accelerators, the same design logic is visible in Tempus Core. Unary-based PE arrays are presented as area-power efficient, but their practical adoption depends on compatibility with existing DLA dataflow. Tempus Core therefore uses tub multipliers that maintain NVDLA dataflow compliance while leveraging temporal-unary behavior for efficiency (Vellaisamy et al., 2024).

A broader representational perspective appears in unary positional encoding. That work frames hybridization not only as a circuit partitioning strategy but also as a number-representation strategy: unary contributes flat error tolerance, while positional encoding contributes compactness. This suggests that hybrid unary-binary architecture is not restricted to MAC arrays; it can also be understood as a general design principle for balancing robustness, compactness, and implementation cost (Zhai et al., 2020).

2. Representations and arithmetic models

A central unary representation in the printed-classifier design maps normalized inputs $x \in [0,1]$ to an $N$-bit unary word $u=(u_1 \ldots u_N)$ according to

$$u_i = \begin{cases} 1, & i \le \lfloor N\,x \rfloor,\ 0, & \text{else.} \end{cases}$$

The corresponding real-valued estimate is

$\hat{x} = \frac{1}{N}\sum_{i=1}^{N} u_i.$

This is a fully parallel unary representation rather than a temporal stream. In the PE setting, that distinction is important because the input can be taken directly from a flash ADC in thermometer code and presented as a unary word without encoder overhead (Armeniakos et al., 18 Sep 2025).

Temporal-unary variants encode magnitude over cycles rather than space. In tubGEMM, an unsigned value $x \in [0, 2^b-1]$ is encoded in ordinary temporal-unary form as

$U_1(x) = 1^x \cdot 0^{(2^b-1)-x}.$

To reduce latency, tubGEMM introduces twos-unary encoding. Writing

$x = 2\cdot \lfloor x/2 \rfloor + (x \bmod 2),$

it defines

$$U_2(x) = 1^{\lfloor x/2 \rfloor}\cdot 0^{2^{b-1}-\lfloor x/2 \rfloor},$$

and emits an odd flag in the final cycle iff $x$ is odd. The processing element adds the binary operand once per unary cycle, corresponding to multiplication by $N$0, plus one additional addition when the odd flag is set (Vellaisamy et al., 2024).

Tempus Core uses a directly analogous 2s-unary formulation for convolution. A parallel INT-$N$1 feature value $N$2 is encoded into a bit-serial stream $N$3 over $N$4 cycles, where $N$5 in the worst case and

$N$6

With a binary weight $N$7, the PE performs

$N$8

so that after $N$9 cycles

$u=(u_1 \ldots u_N)$0

The result is exact multiplication, but with a multi-cycle realization (Vellaisamy et al., 2024).

Unary positional encoding generalizes hybridization at the representational level. For unary length $u=(u_1 \ldots u_N)$1 and number of streams $u=(u_1 \ldots u_N)$2, any integer value $u=(u_1 \ldots u_N)$3 in the range $u=(u_1 \ldots u_N)$4 is represented by $u=(u_1 \ldots u_N)$5 parallel unary streams, each weighted positionally:

$u=(u_1 \ldots u_N)$6

In the temporal-rate spiking realization, the decoded value is

$u=(u_1 \ldots u_N)$7

Here unary coefficients are conveyed by spike counts or rate, while stream weights are conveyed by temporal order. The formulation explicitly trades between unary and positional extremes in latency and error sensitivity (Zhai et al., 2020).

3. Printed-machine-learning realization

The most explicit hybrid unary-binary architecture in the provided literature is the printed MLP classifier proposed for multiplier-less PE implementation. Its defining decision is to keep the first, input layer in fully-parallel unary form and to convert to compact fixed-point binary after that layer. The stated purpose is twofold: removing costly binary encoders by exploiting direct flash-ADC-to-unary mapping, and ensuring that deeper layers use standard adders and comparators with very few multipliers or only power-of-two shifts (Armeniakos et al., 18 Sep 2025).

The high-level datapath is:

Sensor $u=(u_1 \ldots u_N)$8 Flash ADC (thermometer code) $u=(u_1 \ldots u_N)$9 Unary-encoded input word $$u_i = \begin{cases} 1, & i \le \lfloor N\,x \rfloor,\ 0, & \text{else.} \end{cases}$$0 Unary multiplier bank (bitwise-AND/route) $$u_i = \begin{cases} 1, & i \le \lfloor N\,x \rfloor,\ 0, & \text{else.} \end{cases}$$1 Index-to-binary converter $$u_i = \begin{cases} 1, & i \le \lfloor N\,x \rfloor,\ 0, & \text{else.} \end{cases}$$2 Binary accumulator $$u_i = \begin{cases} 1, & i \le \lfloor N\,x \rfloor,\ 0, & \text{else.} \end{cases}$$3 ReLU $$u_i = \begin{cases} 1, & i \le \lfloor N\,x \rfloor,\ 0, & \text{else.} \end{cases}$$4 Subsequent binary layers $$u_i = \begin{cases} 1, & i \le \lfloor N\,x \rfloor,\ 0, & \text{else.} \end{cases}$$5 Comparator tree $$u_i = \begin{cases} 1, & i \le \lfloor N\,x \rfloor,\ 0, & \text{else.} \end{cases}$$6 Class output

The major components are specialized to that partitioning. The Unary Input Generator takes an $$u_i = \begin{cases} 1, & i \le \lfloor N\,x \rfloor,\ 0, & \text{else.} \end{cases}$$7-bit thermometer code directly from a flash ADC and presents it as a parallel unary word. The Unary Constant Multiplier Bank instantiates, for each hidden-layer neuron, a bank of $$u_i = \begin{cases} 1, & i \le \lfloor N\,x \rfloor,\ 0, & \text{else.} \end{cases}$$8 AND gates or direct wires that combine unary input bits with hard-wired unary weight bits; zeros in the weight vector remove AND gates entirely. Index/Count Extraction then uses the positions of ones in the $$u_i = \begin{cases} 1, & i \le \lfloor N\,x \rfloor,\ 0, & \text{else.} \end{cases}$$9-bit result to drive a small binary adder or indexed accumulator, i.e., the count of ones is the dot-product result. After that, Binary Accumulator & ReLU convert the computation into fixed-point binary, and the Hidden/Output Layers use standard binary logic, concluding with a small comparator tree (Armeniakos et al., 18 Sep 2025).

This organization is hybrid in a strong architectural sense rather than merely representational. Unary is used only where PE hardware benefits directly from sensor-interface alignment and multiplier elimination. Binary is used where network depth would otherwise amplify unary overhead. The paper’s discussion identifies this partition as a sweet spot: thermometer-to-unary for inputs, binary thereafter. A plausible implication is that the architecture treats unary not as a universal replacement for binary arithmetic, but as a localized substrate for the most interface-dominated portion of the computation.

4. Multiplier-less execution and architecture-aware training

In the printed MLP, first-layer multiplication is reformulated as unary coincidence counting. For $\hat{x} = \frac{1}{N}\sum_{i=1}^{N} u_i.$0, with unary encodings $\hat{x} = \frac{1}{N}\sum_{i=1}^{N} u_i.$1 and $\hat{x} = \frac{1}{N}\sum_{i=1}^{N} u_i.$2, the dot-product

$\hat{x} = \frac{1}{N}\sum_{i=1}^{N} u_i.$3

is approximated by

$\hat{x} = \frac{1}{N}\sum_{i=1}^{N} u_i.$4

The logic interpretation is direct. If $\hat{x} = \frac{1}{N}\sum_{i=1}^{N} u_i.$5, the corresponding AND gate is eliminated entirely; if $\hat{x} = \frac{1}{N}\sum_{i=1}^{N} u_i.$6, the input bit is passed directly to the count. The design therefore removes any conventional multi-bit multiplier in the first layer. First-layer weights are converted offline into unary constant bit-patterns of length $\hat{x} = \frac{1}{N}\sum_{i=1}^{N} u_i.$7 and hard-wired in the PE fabric (Armeniakos et al., 18 Sep 2025).

The deeper binary layers are then optimized by architecture-aware training. Each weight $\hat{x} = \frac{1}{N}\sum_{i=1}^{N} u_i.$8 is quantized to its nearest power-of-two value $\hat{x} = \frac{1}{N}\sum_{i=1}^{N} u_i.$9. After one such quantization step, that layer alone is retrained for $x \in [0, 2^b-1]$0 epochs while all other layers are fixed, and classification accuracy is measured. If the drop exceeds a preset threshold $x \in [0, 2^b-1]$1, the quantization is rolled back. The procedure repeats until no further quantization is possible without violating accuracy. The paper states that no new loss function is introduced, but that the process effectively enforces a hard regularization on weights so that the final model uses a large fraction of power-of-two weights, minimizing real multipliers (Armeniakos et al., 18 Sep 2025).

This combination of unary first-layer execution and power-of-two binary deeper-layer execution explains the paper’s description of the classifier as multiplier-less. In the first layer, multiplication reduces to AND-plus-count. In later layers, conventional fixed-point multiplies are largely replaced by wiring when weights are quantized to powers of two, so each multiply reduces to a fixed shift or even a direct wire. The term therefore refers to the removal or near-removal of conventional multi-bit multipliers, not to the absence of arithmetic accumulation.

5. Quantitative behavior across representative implementations

The empirical literature shows that hybrid unary-binary design is primarily evaluated through area, power, energy, latency, and accuracy trade-offs. The reported effects vary strongly with domain, precision, and whether unary is spatial/parallel or temporal/serial.

In printed classifiers, the baseline consists of exact 3-bit input/5-bit weight parallel binary MLPs, with average area $x \in [0, 2^b-1]$2 and average power $x \in [0, 2^b-1]$3. The hybrid unary-binary design without power-of-two training reports average area reduction of $x \in [0, 2^b-1]$4, average power reduction of $x \in [0, 2^b-1]$5, and average accuracy loss of $x \in [0, 2^b-1]$6, with accuracy loss $x \in [0, 2^b-1]$7 on all but one dataset. Enabling power-of-two training adds $x \in [0, 2^b-1]$8 area gain and $x \in [0, 2^b-1]$9 power gain with additional accuracy loss $U_1(x) = 1^x \cdot 0^{(2^b-1)-x}.$0. Against approximate binary state-of-the-art, the full design achieves on average $U_1(x) = 1^x \cdot 0^{(2^b-1)-x}.$1 lower area and $U_1(x) = 1^x \cdot 0^{(2^b-1)-x}.$2 lower power for $U_1(x) = 1^x \cdot 0^{(2^b-1)-x}.$3 maximum accuracy drop across six UCI datasets: Cardio, RedWine, WhiteWine, Seeds, Vertebral, and Balance Scale. The discussion states that all operations are fully parallel, producing one inference per cycle at $U_1(x) = 1^x \cdot 0^{(2^b-1)-x}.$4 (Armeniakos et al., 18 Sep 2025).

In tubGEMM, the key comparison is against uGEMM. For 16×16, 8-bit, 45 nm, the reported figures are $U_1(x) = 1^x \cdot 0^{(2^b-1)-x}.$5, $U_1(x) = 1^x \cdot 0^{(2^b-1)-x}.$6, $U_1(x) = 1^x \cdot 0^{(2^b-1)-x}.$7, and $U_1(x) = 1^x \cdot 0^{(2^b-1)-x}.$8 for uGEMM, versus $U_1(x) = 1^x \cdot 0^{(2^b-1)-x}.$9, $x = 2\cdot \lfloor x/2 \rfloor + (x \bmod 2),$0, $x = 2\cdot \lfloor x/2 \rfloor + (x \bmod 2),$1, and $x = 2\cdot \lfloor x/2 \rfloor + (x \bmod 2),$2 for tubGEMM. This corresponds to approximately $x = 2\cdot \lfloor x/2 \rfloor + (x \bmod 2),$3 area savings, $x = 2\cdot \lfloor x/2 \rfloor + (x \bmod 2),$4 power savings, and $x = 2\cdot \lfloor x/2 \rfloor + (x \bmod 2),$5 energy savings, with increased latency. At 5 nm for a 128×128 array, the 8-bit design reports $x = 2\cdot \lfloor x/2 \rfloor + (x \bmod 2),$6, $x = 2\cdot \lfloor x/2 \rfloor + (x \bmod 2),$7, $x = 2\cdot \lfloor x/2 \rfloor + (x \bmod 2),$8 worst-case latency, and $x = 2\cdot \lfloor x/2 \rfloor + (x \bmod 2),$9 worst-case energy; lowering precision to 4 and 2 bits further reduces area, power, and energy. The paper also reports that typical sparsity in MobileNetv2 and ResNet-50 reduces energy by more than $$U_2(x) = 1^{\lfloor x/2 \rfloor}\cdot 0^{2^{b-1}-\lfloor x/2 \rfloor},$$0 (Vellaisamy et al., 2024).

In Tempus Core, post-synthesis INT8 single-cell results at 45 nm and 250 MHz report binary cell area $$U_2(x) = 1^{\lfloor x/2 \rfloor}\cdot 0^{2^{b-1}-\lfloor x/2 \rfloor},$$1 and power $$U_2(x) = 1^{\lfloor x/2 \rfloor}\cdot 0^{2^{b-1}-\lfloor x/2 \rfloor},$$2 versus tub cell area $$U_2(x) = 1^{\lfloor x/2 \rfloor}\cdot 0^{2^{b-1}-\lfloor x/2 \rfloor},$$3 and power $$U_2(x) = 1^{\lfloor x/2 \rfloor}\cdot 0^{2^{b-1}-\lfloor x/2 \rfloor},$$4, i.e., area reduction $$U_2(x) = 1^{\lfloor x/2 \rfloor}\cdot 0^{2^{b-1}-\lfloor x/2 \rfloor},$$5 and power reduction $$U_2(x) = 1^{\lfloor x/2 \rfloor}\cdot 0^{2^{b-1}-\lfloor x/2 \rfloor},$$6. For an INT8 16×16 PE array, binary area is $$U_2(x) = 1^{\lfloor x/2 \rfloor}\cdot 0^{2^{b-1}-\lfloor x/2 \rfloor},$$7 and power $$U_2(x) = 1^{\lfloor x/2 \rfloor}\cdot 0^{2^{b-1}-\lfloor x/2 \rfloor},$$8, while tub area is $$U_2(x) = 1^{\lfloor x/2 \rfloor}\cdot 0^{2^{b-1}-\lfloor x/2 \rfloor},$$9 and power $x$0, i.e., area reduction $x$1 and power reduction $x$2. At the unit level, the PE Cell Unit yields $x$3 and $x$4 reductions in area and power consumption, respectively, over NVDLA’s CMAC unit for INT8 precision. Because the PE is smaller, the paper reports $x$5 and $x$6 iso-area throughput improvements for INT8 and INT4 precisions (Vellaisamy et al., 2024).

Design	Setting	Reported result
Printed hybrid MLP	Six UCI datasets	$x$7 lower area, $x$8 lower power, $x$9 maximum accuracy drop
tubGEMM	16×16, 8-bit, 45 nm vs uGEMM	$N$00 smaller area, $N$01 lower power, $N$02 lower energy
Tempus Core	INT8 PCU vs NVDLA CMAC	$N$03 lower area, $N$04 lower power

Taken together, these results indicate that hybrid unary-binary architectures do not have a single fixed performance profile. In fully parallel printed-classifier form, they can preserve one-inference-per-cycle behavior. In temporal-unary GEMM and convolution form, they usually exchange latency for area and power. This suggests that the benefit is architecture-dependent rather than intrinsic to the representation alone.

6. Variants, trade-offs, and recurring misconceptions

Several distinct hybridization patterns appear in the literature. The printed MLP keeps the first layer in fully parallel unary form and converts to binary afterward. tubGEMM streams one operand in temporal-unary form and keeps the other in binary, using a gated accumulator for exact arithmetic. Tempus Core uses a bit-serial temporal-unary datapath for activations and a compact binary datapath for weights, while preserving the NVDLA inner-product convolution loops. Unary positional encoding combines unary counts with positional weighting, and in spiking form uses timing for stream position and rate for unary coefficient (Armeniakos et al., 18 Sep 2025, Vellaisamy et al., 2024, Vellaisamy et al., 2024, Zhai et al., 2020).

One common misconception is that unary or hybrid unary-binary computing is necessarily approximate or stochastic. The data do not support that generalization. tubGEMM is explicitly described as exact, not approximate, GEMM, and Tempus Core derives exact equality between accumulated temporal-unary products and binary multiplication. By contrast, the printed MLP’s first-layer dot-product is written as an approximation because unary encoding represents real values through finite-length counts (Vellaisamy et al., 2024, Vellaisamy et al., 2024, Armeniakos et al., 18 Sep 2025).

A second misconception is that hybridization always removes latency penalties. The literature presents a more conditional picture. The printed PE classifier is fully parallel and produces one inference per cycle at 20 Hz. However, tubGEMM latency scales with unary pulse length $N$05 per outer step, and Tempus Core uses worst-case tub cycle count $N$06, which is higher than one-cycle binary MAC. The gain is therefore often area-power efficiency rather than absolute latency (Armeniakos et al., 18 Sep 2025, Vellaisamy et al., 2024, Vellaisamy et al., 2024).

A third misconception is that hybrid unary-binary architecture automatically implies programmability. In the printed MLP, the methodology assumes hard-wiring of unary weights after offline conversion; the paper states that fully programmable PE would reintroduce encoders. This restriction is not present in the same form in tubGEMM or Tempus Core, where the hybridization is tied to streamed operands and PE-array organization rather than hard-wired unary constants (Armeniakos et al., 18 Sep 2025, Vellaisamy et al., 2024, Vellaisamy et al., 2024).

The trade-offs are stated explicitly in several works. The printed-classifier paper identifies a sweet spot between pure-unary and pure-binary: pure-unary would bloat bit-streams, whereas pure-binary would incur large multipliers and ADCs. Tempus Core states that hybrid unary-binary convolution wins in ultra-area-constrained designs, at very low precision, or under high sparsity and low dynamic range, but that pure binary wins in low-sparsity, higher-precision regimes and when latency-critical one-shot operations are required. Unary positional encoding similarly presents a bounded intermediate point between unary’s worst-case error of $N$07 and pure binary’s exponential sensitivity to MSB error (Armeniakos et al., 18 Sep 2025, Vellaisamy et al., 2024, Zhai et al., 2020).

A plausible implication is that “hybrid unary-binary architecture” is best understood not as a single canonical circuit template but as a family of representation-placement strategies. What remains invariant is the design rule: unary encoding is introduced only where it collapses expensive arithmetic or interface logic, while binary encoding is preserved where depth, accumulation, storage, or routing favor compact positional representation.