Hardwired-Neurons LPU: Neuromorphic Architectures

• Hardwired-Neurons LPU is a neuromorphic system defined by fixed neuron and synapse wiring that emulates biological circuit modularity.
• Key features include device-level synaptic emulation using SmNiO₃ devices, memristor-based spiking networks, and digital population processors.
• The architecture supports scalable, low-power computation with real-time learning, applicable to robotics, AI inference, and sensory processing.

Hardwired-Neurons Local Processing Unit (LPU) architectures are specialized systems in which neurons and synapses are physically implemented with fixed, deterministic interconnections, offering parallel information processing capabilities reminiscent of biological neural circuits. These architectures span device-level neuromimetic implementations, memristor-based networks, population-based digital neuromorphic processors, and large-scale cognitive substrates such as Hardwired-Neurons Language Processing Units (HNLPU). The following sections survey the principles, device technology, computational modeling, network organization, and scalability underlying the concept of Hardwired-Neurons LPUs.

1. Fundamental Principles and Biological Analogues

A Hardwired-Neurons LPU is characterized by the "hardwiring" of neurons and synapses—fixed physical mapping of functional units and their connectivity, either in silicon, molecular, or biomimetic electronic substrates. This approach draws upon the modularity observed in biological neural circuits, especially the local processing units revealed in connectomic analyses (e.g., Drosophila brain (Shi et al., 2015)). In these biological LPUs, communities of local interneurons show dense intracommunity connectivity and sparse intercommunity links, enabling region-specific processing and hierarchical organization. Hardwired electronic implementations seek functional analogues via monolithic integration at device, circuit, or architectural scales, with the goal of high-throughput, low-power, and adaptive computation.

2. Device-Level Neuromimetic Implementation

Rare-earth nickelate synaptic devices, notably SmNiO₃ gated by ionic liquid, exemplify direct hardware emulation of classical synaptic behavior (Ha et al., 2014). At the device level, resistance modulation mimics long-term potentiation/depression (LTP/LTD) through voltage-induced changes in oxygen stoichiometry. The time-dependent current, captured by the Cottrell equation ($i(t) = \frac{n F A D_o^{1/2} C_O}{\sqrt{t}}$), and voltage-dependent current, captured by the Butler–Volmer equation ($i = i_0 [\exp(\frac{n e \eta}{k_B T}) - 1]$), jointly model ionic-electronic transport. The time- and voltage-coupled resistance is described as:

$$R(V_D, t) = \left( A + B \left( e^{C(V + V_o)} - 1 \right) t^{1/2} - p_c \right)^2 \Omega_m (1 - p_c)^2$$

where $A$, $B$, $C$, $V_0$ are fitting parameters and $p_c$ is the percolation threshold.

These device-level synapses are organized with neuron-mimetic circuits to support associative and non-associative learning, including classical conditioning and extinction. Their passive, low-power operation and analog weight control enable scalable, parallel LPUs with biomimetic learning and adaptation capabilities.

3. Memristor-Based Spiking Networks and Evolutionary Organization

Unipolar memristor synapses employ binary, non-Hebbian switching between low- and high-resistance states, activated after a programmable number of pre/post-synaptic spike coincidences (Howard et al., 2015). The switching rule is summarized as:

• If the coincidence event counter $S_c$ reaches sensitivity $S_n$, toggle the synaptic weight and reset $S_c$.

This binary "weight oscillator" paradigm limits the effective attractor state space, facilitating rapid evolutionary optimization via self-adaptive genetic algorithms ($\mu \rightarrow \mu \cdot \exp(N(0,1))$ for mutation rate adaptation). The result is robust neuromorphic controllers that evolve more rapidly than analog or constant-weight systems, particularly in robotics tasks involving environmental adaptation. The simplicity and manufacturing reliability of unipolar devices make them attractive for large-scale LPU integration.

4. Digital Neuromorphic Processors and Population-Based Organization

Digital implementations, such as the POPPINS architecture (Yeh et al., 2022), hardwire neuron populations using integer quadratic integrate-and-fire (I-QIF) models. Each neuron computes its membrane potential $V_m$ with hardware-friendly equations:

• Conditional stage 1: $V_m[t] = a (V_r - V_m[t-1]) + I[t]$ if $V_m[t-1] < V_{\text{pde,th}}$
• Conditional stage 2: $A V_m = b (V_m[t-1] - V_t) + I[t]$
• Reset: If $V_m[t-1] + 4V_m > V_{\text{max}}$, set $V_m[t] \rightarrow V_{\text{reset}}$

Population hierarchy—configurable subgroups with recurrent intra-group links and uni-directional inter-group pathways—offers improved efficiency ($3.16\times$ speedup) and scalability. POPPINS mimics neuroanatomical motifs, enabling energy-efficient, low-latency inferencing for embedded and robotic applications.

5. Cognitive Substrates: Hardwired-Neurons Language Processing Units

HNLPU advances the hardwired neuron concept by embedding the entirety of LLM weights into the physical computational substrate (Liu et al., 22 Aug 2025). Instead of dynamic memory fetches, parameters are "etched" into the metal interconnect topology (Metal-Embedding methodology). For 4-bit precision, $2^4=16$ unique weight regions are created per neuron, and inputs are routed accordingly. Population count (POPCNT) operations on bit-serialized inputs allow grouping multiple constant multiplications.

The primary technical advantages include a $15\times$ density increase, $112\times$ reduction in photomask set cost (with 60 of 70 mask layers made homogeneous), and significant improvements in throughput (up to 249,960 tokens/s; $5,555\times$ vs. GPU), energy efficiency (36 tokens/J; $1,047\times$ vs. GPU), and carbon footprint ($230\times$ reduction). Metal-Embedding mitigates the otherwise prohibitive non-recurring engineering cost for hardwiring all LLM parameters, and supports annual model updating via limited re-spin costs.

6. Network Theory, Hierarchical Mapping, and Structural Insights

Network-theoretic approaches reveal and quantify LPUs in biological brains (Shi et al., 2015). By representing neuron networks as weighted graphs, and using modularity maximization and participation coefficient $P_i = 1 - \sum_{j=1}^N (S_{ij}/S_i)^2$, researchers automatically delineate dense local communities (LPUs) and segregate long-range projection neuron tracts. Hierarchical iterative detection identifies both canonical LPUs and functional subdivisions (e.g., layered fan-shaped body structures). This objective, non-subjective methodology informs engineered LPU designs with formal principles of modularity, integration, and specialization.

7. Scalability, Adaptivity, and Real-world Applications

Hardwired-Neurons LPUs are inherently scalable, supporting massive parallelism via passive synapse operation, analog/digital integration, and locally parameterizable weights. Adaptive behavior is realized via real-time synaptic plasticity (e.g., device-mediated Hebbian/unlearning cycles, memristor-based STDP, latency coding), and hierarchical population scheduling. Applications span robotics, sensory processing, rapid inference workloads, embedded control, and the deployment of general-purpose cognitive substrates for AI inference.

Table: Representative Hardwired-Neuron LPU Technologies

Technology Area	Key Mechanisms	Principle Applications
Neuromimetic Circuits (Ha et al., 2014)	SNO device plasticity, biologically inspired learning	Parallel adaptive computation, memory storage
Unipolar Memristor Networks (Howard et al., 2015)	Binary switching, evolutionary optimization	Fast-evolving controllers, robustness
Digital Population Processors (Yeh et al., 2022)	I-QIF model, hierarchical populations	Low-power embedded inference, biomimetic processing
HNLPU (Liu et al., 22 Aug 2025)	Metal-embedding, constant arithmetic	LLM inference, general cognitive substrate
Network-Theoretic Detection (Shi et al., 2015)	Modularity, participation coefficient	Mapping and organization of LPUs

In sum, Hardwired-Neurons LPUs span device physics to system architecture, encompassing both biologically inspired hardware and computationally specialized cognitive substrates. Their parallelism, low power, direct circuit implementation, and capacity for real-time learning/adaptation enable new modalities in neuromorphic engineering, large-scale AI inference, and biological modelling. These platforms operationalize the principle that fixed, deterministic wiring—when paired with local adaptivity and hierarchical modularity—yields tractable, powerful substrates for advanced neural information processing.