FuseFlow: Sparse Deep Learning Compiler

• FuseFlow is a compiler framework that fuses sparse tensor operations for deep learning on reconfigurable architectures, maximizing computational efficiency.
• It employs an end-to-end pipeline—from frontend parsing to factored-iteration lowering—to transform high-level models into optimized streaming dataflow graphs.
• Advanced optimizations like parallelization, sparsity blocking, and heuristic pruning drive significant performance gains, with speedups up to 3.9× on key models.

FuseFlow refers to multiple rigorously defined frameworks in contemporary research, spanning domains from sparse machine learning compilation for reconfigurable hardware, to optimal flow estimation in process engineering, and invertible neural flow models for shape correspondence. This article focuses primarily on the fusion-centric compilation framework for sparse deep learning on streaming dataflow architectures, with direct reference to the original research. Distinct usages in other domains are outlined for context.

1. Conceptual Definition and Motivations

FuseFlow is a compiler framework that generates highly optimized fused dataflow graphs from high-level sparse deep learning models, primarily targeting reconfigurable dataflow architectures (RDAs) (Lacouture et al., 6 Nov 2025). The central design motivation is to expose and exploit cross-expression fusion—fusing sparse tensor operations both within and across kernel boundaries—to maximize computational efficiency and hardware utilization. Traditional compilers for sparse tensor algebra support only intra-expression iteration fusion and impose global iteration orders, leading to severe inefficiencies (“coordinate-explosion,” high memory traffic) in multi-layer models and large-scale inference. FuseFlow bridges this gap by (a) supporting general inter-expression kernel fusion (EKF) and (b) offering fine-grained user control over fusion granularity, scheduling, parallelization, and blocking.

RDAs, such as those in Onyx and Capstan, provide native streaming dataflow primitives aligned with sparse computation. Traditional accelerators for deep models (esp. GNNs, sparse Transformers) operate at sub-20% SM/DRAM efficiency due to irregularities in sparsity. FuseFlow is designed to eliminate these bottlenecks, for both research and production hardware.

2. End-to-End Compilation Pipeline

The FuseFlow pipeline consists of the following stages (Lacouture et al., 6 Nov 2025):

1. Frontend Parsing: A PyTorch model, possibly annotated with sparse formats (CSR, block-CSR), is translated via MLIR-based infrastructure to a set of Einsum-like tensor expressions.
2. Cross-Expression Fusion: Users define regions to fuse (Fuse{}). FuseFlow inlines producer kernels into consumers across these boundaries by:
   • Renaming reduction indices to prevent collisions,
   • Building and maintaining a Partial-Order Graph (POG) over index variables (enforcing per-tensor storage order, per-kernel dataflow order, and producer→consumer dependencies),
   • Detecting and resolving cycles via permutation (transpose insertion).
   • Emitting fully fused Einsum expressions for each connected fusion region.
3. Fusion Tables: The compiler constructs a two-dimensional fusion-table intermediate representation (rows = index variables/value, columns = tensor operands & intermediates). Each cell is either a primitive (e.g., level-scanner, intersecter, ALU, reducer) or a reference for stream/data reuse. This enables deferred, grid-centric schedule transformations.
4. Factored-Iteration Lowering: Tables are traversed top-down to emit SAMML primitives and build the dataflow subgraphs. This avoids a global multidimensional iteration nest, instead chaining smaller binary operation subgraphs through pipelined streams.
5. Schedule-Guided Optimizations: The pipeline supports parallelism (via loop or block replication), block-sparsity tiling, and alternate dataflow orders. A fast heuristic is used to prune fusion/dataflow configurations unlikely to be optimal.
6. Backends: The lowered graph can be simulated via Comal for cycle-accuracy, mapped to FPGAs, or targeted at ASIC RDA implementations.

3. Cross-Expression Fusion Algorithms and Factored Iteration

FuseFlow introduces general inter-expression kernel fusion (EKF) as a superset of two traditional approaches:

• Pattern-based operator fusion (POF): Template-driven, local operator fusions common in dense graphs.
• Intra-expression iteration fusion (IIF): Fusion within a single Einsum operation (e.g., in SpMV).
• Inter-expression kernel fusion (EKF): Fusion across multiple chained sparse expressions, previously unsupported in sparse dataflow compilers.

The EKF algorithm maintains global correctness by systematically freshening reduction indices, handling multiple views, and resolving index orderings through the partial-order graph. When mode-orders conflict (e.g., two consumers requiring different storage index orders), the compiler inserts transposes to break cycles. Global index order ($\pi$) is determined by topological sorting of the POG. After fusion, reduction and ALU stages are “factored” such that binary operations are grouped into small-pipeline subgraphs. This reduces coordinate-token and buffer traffic dramatically compared to a single, large, fully-fused iteration nest.

4. Performance Optimizations and Fusion Granularity

FuseFlow provides multiple axes of optimization for fused sparse computation:

• Parallelization: Annotation of index variables with parallel factors enables the compiler to partition the coordinate space and replicate subgraphs accordingly, supporting nested parallelism at multiple loop levels.
• Sparsity Blocking: For block-sparse tensors (such as BigBird’s $16 \times 16$ blocks), iterations are tiled at the block granularity, treating inner block coordinates as dense for vector ALU execution.
• Dataflow Ordering: Multiple valid topological orders of the POG are explored (or constrained by the user) to minimize indirect memory accesses and buffer pressure; invalid or inefficient orders are pruned early.
• Heuristic Pruning: To avoid full exploration of an exponentially large schedule space, FuseFlow’s heuristic evaluates each candidate configuration for operational intensity ($I = \text{FLOPs}/\text{Bytes}$), discarding those below a configurable threshold or exceeding bandwidth limits. This heuristic achieves $\leq 12\%$ average error and discards over 90% of the design space before simulation.

5. Experimental Evaluation and Empirical Trade-Offs

Extensive evaluation demonstrates FuseFlow’s effectiveness on multiple sparse ML workloads (sparse Autoencoders, GCN, GraphSAGE, GPT-3+BigBird). The principal findings are:

Model / Config	Fusion Type	Max Speedup vs. Unfused Baseline
SAE (ImageNet)	Partial	2.1×
	Full	0.98×
GCN (OGB-Collab)	Partial	2.6×
	Full	1.2×
GraphSAGE (OGB-Mag)	Partial	3.9×
	Full	1.1×
GPT-3 + BigBird Attention	Partial	1.8×
	Full	2.7×

Partial fusion—factored at the operator or layer level—achieves significant speedups by reducing bytes transferred and keeping coordinate/iteration complexity manageable. Full fusion further increases operational intensity but can increase computational redundancy (30–50% higher FLOPs) and buffer requirements, sometimes reducing net performance. The optimal fusion granularity is highly model-dependent; block-sparse deep transformers favor full fusion, while GNNs/autoencoders perform best with partial pipelined fusion (Lacouture et al., 6 Nov 2025).

6. Cycle-Accurate Simulation and Implementation

FuseFlow integrates the Comal cycle-accurate dataflow simulator for precise performance evaluation of fused configurations. The simulator models streaming tokens at the SAMML primitive level and incorporates detailed DRAM access timing via Ramulator 2.0. Validation against FPGA-based RTL yields strong cycle-count correlation ($R^2=0.991$). This enables microarchitectural analyses before hardware synthesis and supports co-design of schedules with hardware memory and compute constraints. The entire stack (SAMML IR, Comal, MLIR passes) is open-source and targets both fixed-point and ASIC-based RDAs.

7. Related Contexts and Alternative Definitions

While the above sections focus on FuseFlow as a compiler for sparse deep learning, the term appears in other technical contexts:

• Data Reconciliation and Allocation in Petroleum Systems: FuseFlow denotes a data-driven, field-proven framework exploiting measurement redundancy to infer flow rates in multiphase petroleum production systems. Here it is structured around four modules: data processing, uncertainty estimation, reconciliation (via constrained weighted least squares), and gross-error detection using the maximum-power test. The approach combines statistical tests and redundancy exploitation for robust, uncertainty-quantified allocation (Sjulstad et al., 2024).
• Shape Correspondence via Neural Flows: In geometric learning, FUSE (or “FuseFlow”) represents both 3D shapes and maps between them as distributions induced by continuous invertible flows from a reference Gaussian. This ODE-based framework ensures invertibility, modality-agnostic correspondence across representations, and requires only small per-shape neural vector fields—enabling state-of-the-art, zero-shot shape matching (Olearo et al., 17 Nov 2025).

These usages share nominal terminology but are otherwise technically orthogonal.

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FuseFlow, in the compilation context, establishes a unified infrastructure enabling general cross-expression kernel fusion, fine-grained schedule control, and efficient lowering to factored-iteration dataflow graphs. Its empirical results and open-source ecosystem position it as a foundational platform for future research and deployment in sparse machine learning on configurable hardware (Lacouture et al., 6 Nov 2025).