Fully-Textured Perovskite/Si Tandem Solar Cells
- Fully-textured perovskite/silicon tandem solar cells are photovoltaic devices that use engineered nanostructures to extend the optical path and maximize photocurrent.
- They integrate advanced design and fabrication techniques, such as hexagonal sinusoidal and triangular textures, to approach the Lambertian light-trapping limit.
- The approach balances optical gains with electrical tradeoffs by addressing surface recombination and achieving conformal material deposition for improved device efficiency.
Fully-textured perovskite/silicon tandem solar cells constitute a class of photovoltaic devices in which both the perovskite top cell and the silicon bottom cell are fabricated with engineered surface morphologies—typically periodic submicron or micron-scale texturing—on at least one, and often multiple interfaces. The explicit goal of such texturing is to maximize the optical path length, suppress reflection across the solar spectrum, and approach the Tiedje–Yablonovitch (Lambertian) light-trapping limit, thereby maximizing photocurrent and efficiency in monolithic (2T) or four-terminal (4T) tandem architectures. This approach is distinguished from planar or semi-textured designs by the degree to which the photonic nanostructure is extended through the entire device stack, and the resulting optoelectronic, fabrication, and integration challenges.
1. Nanotexture Geometry, Definition, and Fabrication
The most extensively studied and numerically optimized fully-textured perovskite/silicon tandem architectures employ hexagonal sinusoidal or periodic triangular surface nanotextures at the perovskite interface, silicon interface, or both. A canonical negative-cosine hexagonal sinusoid, over a rhombic unit cell of side length , is defined as: Scaled for arbitrary period and peak-to-valley height via , , and multiplying by , the aspect ratio is . Optimal values are typically , for monolithic configurations (Chen et al., 2018, Jäger et al., 2018).
In alternative designs, periodic isosceles-triangle (2D) textures with period, height, and apex angles – achieve minimal reflectance and current-matching (Hsieh et al., 2023). For mechanical flexibility, microscale random pyramids on c-Si (base widths $5$–m, heights $3$–m) are produced by alkaline etching; perovskite must then conform over these topographies (Sun et al., 29 Apr 2025).
Fabrication techniques for such structures include UV-nanoimprint lithography (sub-m periodic textures), substrate-conformal imprint lithography for Mie-resonant meta-surfaces (Neder et al., 2020), and wet-chemical etching for microscale silicon pyramids (Sun et al., 29 Apr 2025). Conformal vapor or solution-phase deposition of perovskite is essential to preserve texture fidelity, with hybrid two-step or spin-coating demonstrated over nanostructured polymer/glass templates to depths of or greater.
2. Optical Modeling, Current Density, and Light-Trapping Limits
Full-wave 3D finite-element Maxwell solvers (e.g., JCMsuite) rigorously solve for the electromagnetic fields and absorptance in textured, multilayer periodic stacks, with air/silicon modeled as infinite half-spaces using perfectly matched layers. Layer edge-lengths in the mesh are adaptively set to , and the adaptive refinement ensures convergence of , to better than (Chen et al., 2018, Jäger et al., 2018). In RayFlare-based hybrid ray+wave optics simulations, surface scattering is treated via Phong models parameterized by facet inclination and specular/diffuse ratios (Rocha et al., 4 Nov 2025).
Photocurrent density utilization is quantified by: where sums non-active-layer losses. The ultimate limit is set by the Tiedje–Yablonovitch factor.
Lambertian-corrected absorption for finite-thickness (m) silicon is modeled as: This correction is accurate to within against pyramidally textured Si using GenPro4 (Chen et al., 2018, Jäger et al., 2018). For optimal triangular texturing, rigorous coupled-wave analysis (RCWA) solves Maxwell’s curl equations for both TE and TM polarizations and outputs reflected and transmitted powers by diffraction order (Hsieh et al., 2023).
3. Device Performance: Photocurrent, Efficiency, and Loss Mechanisms
The conversion from planar to fully-textured architectures is associated with:
| Metric | Planar | Fully-Textured (Best) |
|---|---|---|
| 19.7 mA/cm² | 21.3 mA/cm² (=500 nm, =500 nm) | |
| 91% | 98% | |
| Reflective losses | 7 mA/cm² | 2 mA/cm² |
| PCE (=81%, typical 's) | 29.3% | 31.8% (+2.5% abs) |
(Chen et al., 2018, Jäger et al., 2018)
In RCWA/Poisson-drift-diffusion co-simulations (Hsieh et al., 2023), optimized texture structure (L=400 nm, H=400 nm) boosts from 17.9 mA/cm² (planar) to 20.87 mA/cm² and PCE from 25.8% to 35.9%. The ultimate scenario, with perovskite carrier lifetime ns and ideal tunnel junctions, projects PCE up to 38.13%.
Angular response is strongly enhanced: current density utilization of 98% is retained up to 50°–60° incidence for fully-textured devices, whereas planar architectures lose >20% at angles >20° (Chen et al., 2018).
4. Texturing Strategies: Full vs. Partial, and Trade-offs
The roles of front, rear, and combined texturing have been systematically dissected. Front-surface texturing acts as a broadband antireflection layer and, above nm, couples near-infrared light into the silicon bottom cell via angular scattering. Rear-surface texturing provides Lambertian light-trapping and reduces parasitic absorption in metallic contacts, particularly above 1000 nm (Rocha et al., 4 Nov 2025).
A critical finding is that fully-textured stacks (front+rear) achieve the best light-trapping and silicon current, but require perovskite texturing, which is associated with surface recombination, inhomogeneous coverage, and voltage losses (–$300$ mV) (Rocha et al., 4 Nov 2025). Back-textured or planar-perovskite designs with only silicon texturing deliver nearly identical (20.8 mA/cm² vs. 21.3 mA/cm²) and overall optical performance, but with substantially reduced recombination penalty ( mV), simplifying fabrication and preserving electrical quality.
Design guidelines from recent simulations recommend: avoid texturing the perovskite surface if mV; keep the perovskite planar and focus on optimized front ARC pyramids (inclination , m, m) and rear (conventional Si pyramids) texturing (Rocha et al., 4 Nov 2025).
5. Materials Integration, Interfacial Engineering, and Mechanical Considerations
Successful fully-textured tandem fabrication requires conformal deposition of perovskite and functional charge-transport, buffer, and recombination layers over steep nanostructures. Spin-coating of perovskite on nanoimprinted sinusoidal substrates yields films with thickness variation for and no significant dewetting; AFM and SEM confirm conformal valleys down to 200 nm (Chen et al., 2018, Jäger et al., 2018). For flexible monolithic tandems, phase homogeneity in the perovskite absorber is essential: FA-only compositions result in uniform 3.42 Å lattice spacing across all pyramid facets, low tensile stress ( MPa vs. 48.7 MPa for mixed-cation), and maintain current-matching and PCE under extreme bending (0.44 cm⁻¹ curvature), with certified PCE=29.88% (1.04 cm²) (Sun et al., 29 Apr 2025).
Integration of transparent conducting oxides (e.g., low-temperature ALD ZnO/ITO) and passivation layers (e.g., SnO₂) must achieve conformal coverage and electrical continuity without shunting or excessive series resistance. Finite element convergence ( level) and cross-verification with alternative optical solvers (GenPro4) ensure accuracy at the design stage.
6. Advanced Optical Concepts and Mie-Resonant Metasurfaces
Beyond sinusoidal and triangular textures, spectral-splitting dielectric metasurfaces provide additional light management options. Mie-resonant metagratings—composed of hexagonal arrays of a-Si:H trimer nanostructures—operate by generating strong diffractive scattering near nm, minimizing specular reflection and enhancing perovskite path length, while transmitting near-IR efficiently to silicon (Neder et al., 2020). Experimental integration in 4T tandems yields a measured increase of 0.5 mA/cm² (+0.26% abs efficiency) for the perovskite cell; simulations project up to +1.4 mA/cm² and +0.4% efficiency in optimized geometries. Such metasurfaces can be directly imprinted onto intermediate TCOs or embedded at perovskite/Si interfaces, offering compatibility with wafer-scale patterning.
7. Efficiency Limitations, Electrical Penalties, and Prospects
Texture-induced electrical losses remain a limitation. Surface recombination at rough perovskite/transport interfaces can impose substantial penalties (–$300$ mV). If fully-textured architecture suffers mV, planar-perovskite tandems with only silicon texturing outperform fully-textured stacks in PCE (up to +0.8% absolute at mV) (Rocha et al., 4 Nov 2025). Tunnel junction engineering and bulk perovskite lifetime ( ns, ideally 100–200 ns) also set ultimate efficiency. Advanced designs project two-terminal efficiencies up to 38.13% with ideal perovskite and junction quality (Hsieh et al., 2023).
Mechanical endurance (flexibility), upscaling (roll-to-roll wet etch, slot-die or blade coating), and cost (<$0.06/W$ silicon, <$0.01/W$ perovskite stack) are now demonstrated at the device level (Sun et al., 29 Apr 2025), supporting the path toward commercialization.
Summary Table: Key Figures for Fully-Textured vs. Planar-Perovskite/Si Tandems
| Architecture | (mA/cm²) | PCE (%) | Loss (mA/cm²) | (mV) |
|---|---|---|---|---|
| Planar (optimized) | ≈19.7 | 29.3 | ≈7 | – |
| Fully-textured (Λ=500 nm) | ≈21.3 | 31.8 | ≈2 | 100–300 |
| Planar-perovskite, Si-textured | 20.8 | ≈32.2 | 2 | ≈50 |
This synthesis demonstrates that fully-textured perovskite/silicon tandems, when optimized for texture geometry and materials integration, can approach or exceed 98% of the theoretical light-trapping limit, pushing current-matched photocurrents to >21 mA/cm² and efficiencies near or above 32%. However, electrical performance is sensitive to texturing strategies; electrical penalties from perovskite texturing may outweigh the incremental optical gain, motivating a preference for planar perovskite in practical high-efficiency designs (Chen et al., 2018, Jäger et al., 2018, Rocha et al., 4 Nov 2025, Hsieh et al., 2023, Sun et al., 29 Apr 2025, Neder et al., 2020).