Fermion-to-Fermion LDPC Codes

• The paper demonstrates that direct fermionic LDPC encoding improves coding rates by storing multiple logical fermions per block.
• The method employs a self-dual CSS construction and Majorana stabilizer framework to ensure fault-tolerant quantum memory with high code rates.
• Numerical benchmarks show that logical error rates scale as p^2, validating the fault-tolerant memory and lattice-surgery transfer protocols.

Searching arXiv for the specified paper and closely related work to ground the article in current research. Fermion-to-fermion low-density parity-check codes are a fault-tolerant coding framework for quantum computation that remains entirely in fermionic degrees of freedom, rather than first mapping fermions to qubits. In the formulation introduced in "Fermion-to-Fermion Low-Density Parity-Check Codes" (Xu et al., 21 Aug 2025), the central idea is a memory–processor architecture: logical fermionic states are stored in a high-rate fermionic LDPC memory, transferred to fermionic color-code processors when logical gates are required, and then returned to memory. The proposal is motivated by the observation that fermion-to-qubit mappings often introduce substantial overhead in operators, connectivity, and circuit depth, whereas a direct fermionic architecture can preserve fermionic structure while improving coding rate by encoding multiple logical complex fermions per block (Xu et al., 21 Aug 2025).

1. Architectural objective and operational model

The framework is designed to move beyond the standard fermion-to-qubit route for simulating fermionic matter. Its stated goal is a fault-tolerant quantum computing architecture that stays entirely in the fermionic world. The architecture has three parts: a fermionic LDPC memory, fermionic color-code processors, and a fermionic interface composed of ancilla fermions. The memory is the main storage block and is intended to encode many logical fermion modes per block; the processors are the active compute blocks where logical operations are carried out; the interface mediates communication between memory and processor (Xu et al., 21 Aug 2025).

Operationally, logical fermionic states are first held in the LDPC memory, then moved into a color-code processor via a measurement-based transfer protocol, where gates are performed fault-tolerantly, and then transferred back. This division of labor is explicit: the paper does not attempt to implement arbitrary logical gates directly within the fermionic LDPC block. Instead, it uses the LDPC code as a high-rate memory and the fermionic color code as the logical-operation layer (Xu et al., 21 Aug 2025).

The comparison class is twofold. First, the proposal is contrasted with fermion-to-qubit mappings, which are said to produce significant overhead from strings of Pauli operators and nonlocality. Second, it is contrasted with earlier fermionic fault-tolerant proposals based on repetition and color codes, where each block encoded only a single logical fermion, leaving the coding rate low. The fermion-to-fermion LDPC approach is therefore organized around a specific claim: encoding multiple logical complex fermions per code block can improve the rate while preserving fermionic structure (Xu et al., 21 Aug 2025).

A plausible implication is that the architecture separates storage efficiency from gate implementation efficiency. The paper states this separation directly in terms of high-rate memory and fault-tolerant processing; the broader systems interpretation is that storage overhead and logical-gate overhead are being optimized by different fermionic code families within one stack.

2. Majorana stabilizer formulation

The codes are defined in the language of Majorana stabilizer codes. Starting from $n$ physical complex fermions, the formalism uses $2n$ Majorana operators

$$\{\gamma_1,\gamma_1',\gamma_2,\gamma_2',\dots,\gamma_n,\gamma_n'\}.$$

Majorana strings form the group

$$\mathrm{Maj}(2n)\equiv\left\{\Gamma=\eta\prod_{j=1}^{n}\gamma_j^{\alpha_j}(\gamma_j')^{\alpha_j'}\;\middle|\; \alpha_j,\alpha_j'\in\{0,1\}\right\},$$

with $\eta\in\{\pm 1,\pm i\}$, and the weight of a Majorana operator is the number of Majorana factors in the string (Xu et al., 21 Aug 2025).

A Majorana stabilizer code is generated by a stabilizer group $\mathcal{S}_{\mathrm{maj}}\subset \mathrm{Maj}(2n)$ whose elements are Hermitian, mutually commuting, even-weight operators, and which excludes $-I$. Logical operators are Majorana strings that commute with all stabilizers but are not themselves stabilizers. In this sense, the fermionic LDPC construction is not merely a translation of qubit LDPC language: it is formulated directly in terms of even-weight stabilizer constraints and fermionic logical operators (Xu et al., 21 Aug 2025).

A crucial fermionic constraint concerns the structure of the logical operators. The logical Majorana operators $\overline{\gamma}_j,\overline{\gamma}'_j$ must have odd weight, and distinct logical Majoranas must have even overlap, so that the encoded operators reproduce the correct fermionic anticommutation relations. The corresponding logical complex fermion creation operator is

$$\overline{c}_j^\dagger=\frac{1}{2}\left(\overline{\gamma}_j+i\overline{\gamma}'_j\right).$$

This condition is a common point of confusion when comparing fermionic and qubit stabilizer constructions: self-duality of the underlying CSS structure is not by itself sufficient for a useful fermionic code. The odd-weight and even-overlap constraints are additional requirements imposed by fermionic statistics (Xu et al., 21 Aug 2025).

3. Systematic construction from self-dual CSS codes

The paper develops a systematic construction of fermionic LDPC memories from self-dual CSS codes. The starting point is a CSS check matrix satisfying

$H_X = H_Z = A,\qquad AA^T=0.$

From this, the authors construct a fermionic Majorana check matrix of block-diagonal form

$2n$0

Here $2n$1 and $2n$2 describe stabilizers made purely of $2n$3 or purely of $2n$4, respectively (Xu et al., 21 Aug 2025).

The logical operators correspond to vectors in

$2n$5

for both $2n$6-type and $2n$7-type logicals. The paper identifies this quotient as the homological structure behind the logical space, in the same sense used in standard CSS and homological coding theory. The resulting fermionic code inherits the sparse-check structure of the underlying classical or CSS-derived code, while its logical fermions are selected by additional fermionic criteria (Xu et al., 21 Aug 2025).

To find the required odd-weight logicals, the construction generalizes Gram–Schmidt orthogonalization over $2n$8. Given a basis $2n$9 of $$\{\gamma_1,\gamma_1',\gamma_2,\gamma_2',\dots,\gamma_n,\gamma_n'\}.$$0, represented as binary vectors, odd-weight basis vectors are isolated, and the remaining vectors are orthogonalized against them using

$$\{\gamma_1,\gamma_1',\gamma_2,\gamma_2',\dots,\gamma_n,\gamma_n'\}.$$1

This is repeated until no odd-weight vectors remain. The resulting odd-weight vectors define fermionic logical operators, and the authors state that the procedure produces a maximally linearly independent set of odd-weight vectors (Xu et al., 21 Aug 2025).

The existence criterion is sharp. A necessary and sufficient condition for the existence of at least one odd-weight logical is

$$\{\gamma_1,\gamma_1',\gamma_2,\gamma_2',\dots,\gamma_n,\gamma_n'\}.$$2

This condition excludes some self-dual CSS codes from yielding useful fermionic codes; the paper specifically notes that the Kitaev Majorana code and unicycle codes do not support the required odd-weight logical operators (Xu et al., 21 Aug 2025).

This suggests that the fermionic construction problem is not identical to the qubit LDPC construction problem. Self-duality and low-density checks provide the ambient structure, but the admissible logical sector is determined by a fermionic parity condition that can invalidate otherwise natural code families.

4. Code families, rate, and LDPC provenance

Using the self-dual CSS method, the paper constructs fermionic LDPC codes from three known LDPC families: bicycle codes, finite Euclidean geometry codes, and finite projective geometry codes. The resulting fermionic subspace codes are described as preserving essentially the same coding rate as the original classical-derived LDPC codes, while achieving much higher rate than the fermionic color code. This is one of the central practical claims of the work, because the memory can encode multiple logical fermions per block rather than just one (Xu et al., 21 Aug 2025).

Examples explicitly mentioned are a finite projective geometry code labeled $$\{\gamma_1,\gamma_1',\gamma_2,\gamma_2',\dots,\gamma_n,\gamma_n'\}.$$3, a finite Euclidean geometry code $$\{\gamma_1,\gamma_1',\gamma_2,\gamma_2',\dots,\gamma_n,\gamma_n'\}.$$4, and a bicycle code $$\{\gamma_1,\gamma_1',\gamma_2,\gamma_2',\dots,\gamma_n,\gamma_n'\}.$$5. These are compared against fermionic color-code baselines. The stated conclusion from the examples is that the fermionic LDPC memory can achieve a much better rate while maintaining useful distance and favorable error-correction behavior (Xu et al., 21 Aug 2025).

The broader LDPC provenance of this construction lies in classical sparse parity-check design. One relevant line of work is the use of structured parity-check matrices built from combinatorial designs, including BIBDs, cyclic BIBDs, resolvable BIBDs, and cyclically resolvable cyclic BIBDs, to obtain high-rate structured LDPC codes with constant column weights and favorable girth properties (Gruner et al., 2012). Another related line is the use of sparse parity-check matrices for fermionic simulation encodings, where classical LDPC or parity-check code structure is used to compress particle-conserved fermionic subspaces (Cheng et al., 2023).

These neighboring developments are not the same as fermion-to-fermion LDPC memories. The combinatorial-design literature addresses classical LDPC and related repeat-accumulate constructions (Gruner et al., 2012), while particle-conserved linear encodings compress fermionic occupation subspaces into qubits using parity-check matrices and classical decoding (Cheng et al., 2023). The fermion-to-fermion LDPC framework differs in target and substrate: it aims at a fault-tolerant architecture that encodes and processes directly in fermionic hardware rather than in a qubit encoding layer (Xu et al., 21 Aug 2025).

5. Fault-tolerant transfer and fermionic lattice surgery

Logical computation is implemented through a memory–processor split. A target logical fermion is transferred from an LDPC memory block $$\{\gamma_1,\gamma_1',\gamma_2,\gamma_2',\dots,\gamma_n,\gamma_n'\}.$$6 into a fermionic color-code processor block $$\{\gamma_1,\gamma_1',\gamma_2,\gamma_2',\dots,\gamma_n,\gamma_n'\}.$$7, logical operations are performed there, and the state is then returned to memory. The core measurement in the transfer protocol is the joint logical operator

$$\{\gamma_1,\gamma_1',\gamma_2,\gamma_2',\dots,\gamma_n,\gamma_n'\}.$$8

In the simplest case, the memory and processor have equal logical Majorana support size $$\{\gamma_1,\gamma_1',\gamma_2,\gamma_2',\dots,\gamma_n,\gamma_n'\}.$$9. The circuit first measures $$\mathrm{Maj}(2n)\equiv\left\{\Gamma=\eta\prod_{j=1}^{n}\gamma_j^{\alpha_j}(\gamma_j')^{\alpha_j'}\;\middle|\; \alpha_j,\alpha_j'\in\{0,1\}\right\},$$0, then measures the logical particle number $$\mathrm{Maj}(2n)\equiv\left\{\Gamma=\eta\prod_{j=1}^{n}\gamma_j^{\alpha_j}(\gamma_j')^{\alpha_j'}\;\middle|\; \alpha_j,\alpha_j'\in\{0,1\}\right\},$$1, with correction gates applied depending on the outcomes. The protocol also uses a $$\mathrm{Maj}(2n)\equiv\left\{\Gamma=\eta\prod_{j=1}^{n}\gamma_j^{\alpha_j}(\gamma_j')^{\alpha_j'}\;\middle|\; \alpha_j,\alpha_j'\in\{0,1\}\right\},$$2 gate defined by

$$\mathrm{Maj}(2n)\equiv\left\{\Gamma=\eta\prod_{j=1}^{n}\gamma_j^{\alpha_j}(\gamma_j')^{\alpha_j'}\;\middle|\; \alpha_j,\alpha_j'\in\{0,1\}\right\},$$3

The paper states that this circuit effectively swaps logical fermionic content between memory and processor while respecting fermionic statistics (Xu et al., 21 Aug 2025).

The fault-tolerant realization of the joint measurement is based on fermionic lattice surgery. The memory and processor are aligned so that the support of $$\mathrm{Maj}(2n)\equiv\left\{\Gamma=\eta\prod_{j=1}^{n}\gamma_j^{\alpha_j}(\gamma_j')^{\alpha_j'}\;\middle|\; \alpha_j,\alpha_j'\in\{0,1\}\right\},$$4 matches $$\mathrm{Maj}(2n)\equiv\left\{\Gamma=\eta\prod_{j=1}^{n}\gamma_j^{\alpha_j}(\gamma_j')^{\alpha_j'}\;\middle|\; \alpha_j,\alpha_j'\in\{0,1\}\right\},$$5, and ancilla Majorana modes are inserted between them: $$\mathrm{Maj}(2n)\equiv\left\{\Gamma=\eta\prod_{j=1}^{n}\gamma_j^{\alpha_j}(\gamma_j')^{\alpha_j'}\;\middle|\; \alpha_j,\alpha_j'\in\{0,1\}\right\},$$6 corresponding to $$\mathrm{Maj}(2n)\equiv\left\{\Gamma=\eta\prod_{j=1}^{n}\gamma_j^{\alpha_j}(\gamma_j')^{\alpha_j'}\;\middle|\; \alpha_j,\alpha_j'\in\{0,1\}\right\},$$7 complex fermions. The boundary $$\mathrm{Maj}(2n)\equiv\left\{\Gamma=\eta\prod_{j=1}^{n}\gamma_j^{\alpha_j}(\gamma_j')^{\alpha_j'}\;\middle|\; \alpha_j,\alpha_j'\in\{0,1\}\right\},$$8-type stabilizers are modified to include ancilla Majoranas, and new measurement stabilizers $$\mathrm{Maj}(2n)\equiv\left\{\Gamma=\eta\prod_{j=1}^{n}\gamma_j^{\alpha_j}(\gamma_j')^{\alpha_j'}\;\middle|\; \alpha_j,\alpha_j'\in\{0,1\}\right\},$$9 and gauge stabilizers $\eta\in\{\pm 1,\pm i\}$0 are introduced, while the $\eta\in\{\pm 1,\pm i\}$1-type stabilizers are left unchanged (Xu et al., 21 Aug 2025).

After merging, the code $\eta\in\{\pm 1,\pm i\}$2 contains the joint stabilizer $\eta\in\{\pm 1,\pm i\}$3, and only one logical complex fermion remains, encoded by the $\eta\in\{\pm 1,\pm i\}$4-type logicals. A key claim is that this merging procedure does not decrease the code distance; the paper says this is shown using the subsystem-code formalism. The ancilla overhead is also described as small compared with the memory block size (Xu et al., 21 Aug 2025).

The general fault-tolerant measurement protocol is given in four steps: initialize ancilla complex fermions in $\eta\in\{\pm 1,\pm i\}$5, measure all stabilizer generators of the merged code, perform $\eta\in\{\pm 1,\pm i\}$6 rounds of error correction under noisy measurement, and then measure the ancilla fermions in the particle-number basis to return to the original code space. This is the interface mechanism that makes memory–processor transfer fault-tolerant (Xu et al., 21 Aug 2025).

6. Numerical benchmarks, demonstration, and limitations

The memory is benchmarked by simulation of a noisy storage process. Each sample uses $\eta\in\{\pm 1,\pm i\}$7 error-correction cycles, and each cycle consists of three layers: random errors, syndrome measurement, and correction. The error model applies physical single-fermion gates $\eta\in\{\pm 1,\pm i\}$8, $\eta\in\{\pm 1,\pm i\}$9, and $\mathcal{S}_{\mathrm{maj}}\subset \mathrm{Maj}(2n)$0 with equal probability $\mathcal{S}_{\mathrm{maj}}\subset \mathrm{Maj}(2n)$1. Syndrome measurements are assumed perfect in this benchmark, and error correction uses belief propagation plus ordered-statistical decoding (BP+OSD) (Xu et al., 21 Aug 2025).

Under this model, the logical failure rate scales roughly as

$\mathcal{S}_{\mathrm{maj}}\subset \mathrm{Maj}(2n)$2

indicating strong suppression of logical error relative to physical error. The paper also defines a pseudo-threshold by the break-even condition

$\mathcal{S}_{\mathrm{maj}}\subset \mathrm{Maj}(2n)$3

where $\mathcal{S}_{\mathrm{maj}}\subset \mathrm{Maj}(2n)$4 is the probability of at least one physical error among $\mathcal{S}_{\mathrm{maj}}\subset \mathrm{Maj}(2n)$5 sites. The three example codes are reported to show relatively high pseudo-thresholds. Within the assumptions of the benchmark, this is presented as evidence that the fermionic LDPC block is an effective noisy memory rather than only a high-rate encoding (Xu et al., 21 Aug 2025).

The full architecture is then illustrated through a simulated fermionic dynamical process involving braid gates, onsite measurements, and conditional fermionic swap operations. The initialized logical state is

$\mathcal{S}_{\mathrm{maj}}\subset \mathrm{Maj}(2n)$6

followed by braid gates

$\mathcal{S}_{\mathrm{maj}}\subset \mathrm{Maj}(2n)$7

and onsite measurements of $\mathcal{S}_{\mathrm{maj}}\subset \mathrm{Maj}(2n)$8 with feedback fSWAP gates when the measurement result is zero. The demonstration uses the $\mathcal{S}_{\mathrm{maj}}\subset \mathrm{Maj}(2n)$9 fermionic LDPC code as memory and two copies of the fermionic Steane code as processors. The tracked observable is $-I$0, which exhibits oscillatory dynamics with a time-averaged value above $-I$1, described as consistent with the expected feedback-induced skin effect / skin-state behavior. The error-corrected trajectory stays very close to the noiseless result, whereas the uncorrected noisy trajectory deviates strongly (Xu et al., 21 Aug 2025).

The limitations are explicit. The memory benchmark assumes perfect syndrome measurements, so its reported performance is optimistic relative to fully noisy hardware. The lattice-surgery construction is first presented for the case in which the processor code distance matches the logical support size of the transferred operator, although the general case where the processor is also an LDPC code is said to be handled in the supplement. The protocol also relies on fermionic hardware capable of programmable operations, ancilla handling, and repeated stabilizer measurements (Xu et al., 21 Aug 2025).

A plausible implication is that the proposal is best understood as an architectural path rather than a finished hardware prescription. Its conceptual significance lies in showing that high-rate fermionic memories, systematic fermionic code construction from self-dual CSS data, and fault-tolerant fermionic interfaces can be combined into a concrete scheme for direct fermionic quantum computation without a fermion-to-qubit mapping layer (Xu et al., 21 Aug 2025).