Fan-In/Fan-Out Systems in Multi-Domain Hardware

• Fan-In/Fan-Out systems are interconnection architectures that aggregate multiple inputs and distribute a single source to numerous outputs across varied hardware platforms.
• They impact performance through key parameters like mode overlap, interference symmetry, repeater overhead, and crosstalk, which influence depth, loss, and routing efficiency.
• Implementations in optical, digital, quantum, spin-wave, and neuromorphic systems show that precise alignment, balanced routing, and physical constraints are critical for optimal performance.

Searching arXiv for the specified papers and closely related fan-in/fan-out research. A fan-in/fan-out system is an interconnection or computational arrangement that aggregates multiple inputs into a shared transport or processing structure and/or distributes one source to multiple outputs. In the cited literature, the term spans optical coupling hardware for multicore fibers, structural constraints in classical logic, constant-depth primitives in quantum circuits, and native multi-output or multi-input behavior in spin-wave, nanomagnetic, and superconducting neuromorphic devices (Ma et al., 19 May 2026, Thomson et al., 2012, Held et al., 2015, Gokhale et al., 2020, Mahmoud et al., 2021, Schneider et al., 2020). Across these domains, fan-in and fan-out are not merely graph-theoretic descriptors: they are tied to mode overlap, interference symmetry, repeater overhead, crosstalk, timing, and physical routing.

1. Definitions and conceptual scope

In binary logic, fan-in is the number of inputs to a gate, while fan-out is the number of gates driven by a single output. The adder literature considered here restricts itself to 2-input gates and emphasizes that fan-outs greater than two typically require balanced repeater trees, adding $\mathcal{O}(1)$ depth and $\mathcal{O}(\text{fan-out})$ extra gates (Held et al., 2015). In Josephson-junction neuromorphic circuits, the terminology is specialized: fan-out $(NFO)$ is the number of synaptic loads to which a single neuronal SFQ pulse can be driven, whereas fan-in $(NFI)$ is the number of weighted input signals summed in the neuron’s input loop and compared to threshold (Schneider et al., 2020).

Optical work uses the term in an interface sense. On the fan-in side of the coaxial dual-core optical fiber device, a single-mode fiber array is mechanically aligned to the central core and annular core of a coaxial dual-core fiber (CDCF); on the network side, a single CDCF end-face is exposed for downstream connection (Ma et al., 19 May 2026). In the 121-waveguide astrophotonic reformater, the device can also operate in reverse by reciprocity: a linear input array of single-mode waveguides can be recombined into a 2D 120-core multicore fiber (Thomson et al., 2012).

This cross-domain usage supports a precise but broad definition: fan-in/fan-out systems are architectures that manage controlled aggregation and replication under physical constraints set by the substrate, signal carrier, and implementation technology.

2. Optical fan-in/fan-out devices

The optical literature in the cited set presents two distinct realizations. One is a coaxial dual-core fiber fan-in device fabricated on a fused-quartz V-groove substrate. Two mutually orthogonal V-grooves hold the CDCF and the associated SMFs so that the SMF cores and CDCF cores lie in the same optical plane, and a flat quartz cover plate locks the fiber positions before UV adhesive curing. The fabrication route is entirely cold: it uses mechanical polishing, alignment, and UV encapsulation, and requires no fusion splicing or thermal processing (Ma et al., 19 May 2026). The first SMF is polished into two $45^\circ$ facets, rotated by $180^\circ$ between polishing steps, and both facets are sputter-coated with a high-reflectivity metal film. The achieved tolerances are within $\pm 0.2^\circ$ of $45^\circ$, with surface roughness sufficient for $>95\%$ reflectivity at $980\,\text{nm}$ (Ma et al., 19 May 2026).

The other optical realization is a three-dimensional 121-waveguide fan-out written by ultrafast laser inscription in a $\mathcal{O}(\text{fan-out})$0 block of Corning EAGLE2000 glass. At the input end, 121 waveguides reproduce the $\mathcal{O}(\text{fan-out})$1 pitch geometry of a 120-core multicore fiber plus one spare; at the output end, the same set is reformatted into a one-dimensional linear array with $\mathcal{O}(\text{fan-out})$2 inter-waveguide pitch. Reformatting is achieved by two orthogonal S-bend segments per waveguide, each with $\mathcal{O}(\text{fan-out})$3 radius (Thomson et al., 2012).

The relevant optical figures are summarized below.

System	Structure	Reported loss figure
CDCF fan-in device	V-groove quartz submount; one polished SMF for the central core and two SMFs for annular-core launch	At $\mathcal{O}(\text{fan-out})$4: average insertion loss $\mathcal{O}(\text{fan-out})$5 for the central core and $\mathcal{O}(\text{fan-out})$6 for the ring core
121-waveguide fan-out	ULI-written 3D reformater from 2D multicore-fiber geometry to 1D linear array	Approximately $\mathcal{O}(\text{fan-out})$7 overall throughput loss with actual MCF; approximately $\mathcal{O}(\text{fan-out})$8 if perfect coupling into the fan-out is achieved

For the CDCF device, coupling efficiency is expressed through the squared overlap integral,

$\mathcal{O}(\text{fan-out})$9

and insertion loss is

$(NFO)$0

Beam-propagation modeling showed that deviations of $(NFO)$1 in the $(NFO)$2 facet angle cause substantial lateral beam shifts and coupling drop-off, while experimental measurements at $(NFO)$3 gave ring-core and central-core insertion losses in close agreement with the design targets (Ma et al., 19 May 2026). For the 121-waveguide device, the paper states that the fan-out alone had $(NFO)$4, with a range of $(NFO)$5–$(NFO)$6 per channel, whereas the fan-out plus MCF had $(NFO)$7, with a range of $(NFO)$8–$(NFO)$9 per channel (Thomson et al., 2012).

A plausible implication is that optical fan-in/fan-out systems are governed by two separable problems: internal reformatting loss and interface loss. The CDCF work attacks the former through mechanical precision and cold assembly, while the ULI reformater shows that external alignment can dominate the total budget even when the underlying fan-out structure is functional (Ma et al., 19 May 2026, Thomson et al., 2012).

3. Fan-out constraints in classical logic networks

In classical digital circuits, fan-out is treated as a primary design constraint because it directly affects repeater insertion, depth, and physical realizability. The adder literature states explicitly that unbounded fan-out can be traded against additional depth and gates by inserting balanced repeater trees, with one unit of depth added for each doubling of fan-out (Held et al., 2015). This is why high-performance designs frequently insist on a fan-out bound of two.

The standard prefix-adders illustrate the trade space. The Kogge–Stone adder has depth $(NFI)$0, size $(NFI)$1, and fan-out $(NFI)$2. Brent’s construction reaches depth $(NFI)$3 for any fixed $(NFI)$4 but gives no explicit fan-out or size bound. Krapchenko’s adder achieves depth $(NFI)$5 and size $(NFI)$6, but can have fan-out up to $(NFI)$7. Brent–Kung preserves fan-out $(NFI)$8 and linear size, but its logic-gate depth is $(NFI)$9 (Held et al., 2015).

The new family in the cited paper integrates a multi-input generate structure with an augmented AND-prefix graph and then applies Brent–Kung size reduction. The resulting adders achieve asymptotically optimum logic-gate depth $45^\circ$0, linear size $45^\circ$1, and fan-out $45^\circ$2 (Held et al., 2015). The paper further states that, for every $45^\circ$3, one can achieve size at most $45^\circ$4 logic gates and depth

$45^\circ$5

while using only 2-input gates (Held et al., 2015).

This literature establishes a recurrent principle: a fan-out system cannot be evaluated only by the abstract connectivity of its graph. Once repeater trees, loading, and layout overhead are included, fan-out becomes a first-order determinant of depth and size.

4. Quantum fan-out as a hardware primitive

In the quantum setting, fan-out is defined both logically and physically. At the logical level, with one control qubit $45^\circ$6 and $45^\circ$7 target qubits $45^\circ$8, fan-out is the product of CNOTs

$45^\circ$9

and has depth $180^\circ$0 under exclusive activation (Gokhale et al., 2020). The same paper states that when the targets start in $180^\circ$1, the logical fan-out copies the classical bit in $180^\circ$2 into each target. At the physical level, platforms with global interactions can realize the same effect in one step. For trapped ions, the primitive is implemented by a global Mølmer–Sørensen interaction,

$180^\circ$3

and with $180^\circ$4 plus single-qubit rotations it realizes all $180^\circ$5 CNOTs in one step (Gokhale et al., 2020).

The paper abstracts this as a single-timestep unitary $180^\circ$6 acting on control $180^\circ$7 and a target set $180^\circ$8, with depth $180^\circ$9, no ancilla, and a single round of a global entangling Hamiltonian (Gokhale et al., 2020). This primitive changes the complexity of larger constructions. A controlled-$\pm 0.2^\circ$0 operation on an $\pm 0.2^\circ$1-qubit data register, where $\pm 0.2^\circ$2 has depth $\pm 0.2^\circ$3, has naive depth $\pm 0.2^\circ$4 if the control qubit must be serialized through separate CNOTs, but can be reduced to $\pm 0.2^\circ$5 depth with fan-out-based synthesis and $\pm 0.2^\circ$6 ancilla. The paper gives the formulas

$\pm 0.2^\circ$7

with the practical $\pm 0.2^\circ$8 cost reported as 5 layers for single-qubit controls and 12 for Toffoli layers (Gokhale et al., 2020).

The same fan-out primitive is used to construct quantum memory architectures. In the explicit QRAM-style design, depth-$\pm 0.2^\circ$9 sequences of fan-out SWAPs reduce latency to $45^\circ$0, compared with $45^\circ$1 for bucket-brigade QRAM or $45^\circ$2 for naive serialization. In the implicit QROM-style design, fan-out reduces latency from $45^\circ$3 to $45^\circ$4 for writing a $45^\circ$5-bit datum, with no extra qubits (Gokhale et al., 2020).

Hardware modeling supports the asymptotic argument. In trapped ions, one GMS pulse of duration $45^\circ$6 realizes the primitive; in superconducting qubits, a multi-tone cross-resonance drive on the control qubit addresses all targets simultaneously. The paper reports a superconducting proof-of-concept for $45^\circ$7 with a depth speedup of $45^\circ$8 and GHZ-test probabilities of $45^\circ$9 for simultaneous fan-out versus $>95\%$0 for serial execution (Gokhale et al., 2020). Its trapped-ion simulations further report a $>95\%$1–$>95\%$2 infidelity reduction at $>95\%$3 under realistic noise, with future hardware yielding up to $>95\%$4 improvement (Gokhale et al., 2020).

A common misconception is that quantum fan-out is simply the unrestricted copying of arbitrary quantum states. The cited formulation is narrower: it copies the classical bit in the control into targets initialized in $>95\%$5, and its practical advantage comes from a platform-specific global interaction rather than from a purely logical rewrite (Gokhale et al., 2020).

5. Wave-based and nanomagnetic realizations

Wave-based fan-out systems implement duplication and aggregation through interference rather than through explicit transistor-level buffering. In the ladder-shaped spin-wave MAJ3 gate, a central horizontal waveguide receives three inputs and branches symmetrically into two outputs. Distances $>95\%$6 are chosen as integer multiples of the spin-wave wavelength $>95\%$7, so that constructive and destructive interference realize majority behavior, with logical $>95\%$8 encoded as phase $>95\%$9 or $980\,\text{nm}$0 (Mahmoud et al., 2021). The paper defines the local spin wave as

$980\,\text{nm}$1

and the superposed output amplitude by

$980\,\text{nm}$2

For identical amplitudes and $980\,\text{nm}$3, the output phase follows the 2-of-3 majority (Mahmoud et al., 2021).

Micromagnetic OOMMF simulations validated the FO2 behavior. The output phase exactly matched the MAJ3 truth table, and the normalized magnetization-spinning angle at the two outputs was identical within $980\,\text{nm}$4, demonstrating negligible amplitude mismatch. The paper states that the proposed FO2 MAJ3 gate occupies $980\,\text{nm}$5, saves approximately $980\,\text{nm}$6 area at gate level relative to duplicating a prior single-output SW MAJ3 gate, and is approximately $980\,\text{nm}$7 more compact than a 15 nm CMOS MAJ3 implementation under the comparison used there (Mahmoud et al., 2021).

The triangle-shaped FO2 spin-wave gates use a different geometry but a similar principle. Three input waveguides feed a triangular focusing region and then split symmetrically into two outputs. The Majority gate uses phase detection and the XOR gate uses threshold detection. For the Fe$980\,\text{nm}$8Co$980\,\text{nm}$9B$\mathcal{O}(\text{fan-out})$00 waveguide parameters given in the paper, the FO2 Majority gate consumes $\mathcal{O}(\text{fan-out})$01 with delay $\mathcal{O}(\text{fan-out})$02, while the FO2 XOR gate consumes $\mathcal{O}(\text{fan-out})$03 with the same delay. Relative to the paper’s comparison set, the triangle-shaped structures reduce energy by $\mathcal{O}(\text{fan-out})$04 for MAJ and $\mathcal{O}(\text{fan-out})$05 for XOR versus ladder-shaped FO2 spin-wave devices, with unchanged delay (Mahmoud et al., 2020).

Nanomagnetic fan-in/fan-out is represented in the cited set by a multiferroic NAND gate implemented with 12 dipole-coupled two-phase multiferroic elements. Two input logic wires couple into a 4-magnet NAND gate, whose outputs couple into three fan-out branches. Magnetization dynamics are modeled by the Landau–Lifshitz–Gilbert equation, thermal fluctuations are neglected, and electrostatic potentials of approximately $\mathcal{O}(\text{fan-out})$06 applied to the piezoelectric layer generate approximately $\mathcal{O}(\text{fan-out})$07 stress in the magnetostrictive layer (Fashami et al., 2011). The paper reports a pipeline bit-throughput rate of approximately $\mathcal{O}(\text{fan-out})$08, gate operation completed in $\mathcal{O}(\text{fan-out})$09, pipeline latency of $\mathcal{O}(\text{fan-out})$10, internal dissipation of approximately $\mathcal{O}(\text{fan-out})$11 in the NAND core, and approximately $\mathcal{O}(\text{fan-out})$12 in the full 12-magnet array comprising fan-in and fan-out wires (Fashami et al., 2011).

These results show that fan-out can be native to interference symmetry or dipole coupling rather than added as an external splitter. At the same time, the papers make clear that such native fan-out is not synonymous with gain. The ladder-shaped spin-wave gate explicitly states that $\mathcal{O}(\text{fan-out})$13 and that overall signal power decays with each stage because no active gain stage is inserted (Mahmoud et al., 2021).

6. Superconducting neuromorphic scaling and cross-domain design rules

In superconducting neuromorphic circuits based on Josephson junctions, fan-out is treated as effectively unbounded in principle and fan-in as substantially more constrained. The cited analysis states that fan-out should be limited only by junction count and circuit size limitations, and WR-SPICE simulations demonstrate 1-to-10,000 fan-out, with a 1-to-16,384 splitter tree also shown in simulation (Schneider et al., 2020). In the flux-based splitter tree, a binary SFQ splitter uses 3 Josephson junctions, so a 1-to-$\mathcal{O}(\text{fan-out})$14 fan-out requires

$\mathcal{O}(\text{fan-out})$15

With example parameters $\mathcal{O}(\text{fan-out})$16, $\mathcal{O}(\text{fan-out})$17, $\mathcal{O}(\text{fan-out})$18, $\mathcal{O}(\text{fan-out})$19, $\mathcal{O}(\text{fan-out})$20, and bias $\mathcal{O}(\text{fan-out})$21, the paper reports 1-to-128 fan-out with approximately $\mathcal{O}(\text{fan-out})$22 latency and approximately $\mathcal{O}(\text{fan-out})$23 (Schneider et al., 2020).

Fan-in is analyzed through current-based and flux-based summation. The current-based scaling is summarized by

$\mathcal{O}(\text{fan-out})$24

which yields a maximum achievable current-based fan-in on the order of 10–20 for the realistic inductances discussed in the paper. The flux-based expression,

$\mathcal{O}(\text{fan-out})$25

scales to much larger values, with maximum $\mathcal{O}(\text{fan-out})$26 on the order of 100–300 for current fabrication parameters (Schneider et al., 2020). The paper also reports reliable 128-to-1 summation for the flux method and only 10-to-1 for the current method in worst-case simulation setups. Crosstalk behaves correspondingly: in the flux method it scales approximately as $\mathcal{O}(\text{fan-out})$27 and is $\mathcal{O}(\text{fan-out})$28–$\mathcal{O}(\text{fan-out})$29 at $\mathcal{O}(\text{fan-out})$30, while in the current method it is much larger, with a predicted $\mathcal{O}(\text{fan-out})$31 at $\mathcal{O}(\text{fan-out})$32 and simulation giving $\mathcal{O}(\text{fan-out})$33 (Schneider et al., 2020).

Several design rules recur across the full set of fan-in/fan-out systems. One is symmetry: identical spin-wave arms yield native FO2, orthogonal V-grooves place optical cores in the same optical plane, and equal path lengths are required to preserve identical delays in Josephson splitter trees (Mahmoud et al., 2021, Ma et al., 19 May 2026, Schneider et al., 2020). A second is resource replication under bounded load: classical adders use balanced repeater trees to enforce fan-out $\mathcal{O}(\text{fan-out})$34, while superconducting splitter trees realize very large fan-out by a regular hierarchy of binary splitters (Held et al., 2015, Schneider et al., 2020). A third is sensitivity to interface mismatch or crosstalk: optical losses are strongly affected by alignment and mode mismatch, and neuromorphic fan-in is constrained by summation-loop impedance and idle-branch signal theft (Thomson et al., 2012, Schneider et al., 2020).

A common misconception is that high fan-out automatically implies efficient replication. The cited literature shows otherwise. In classical logic, larger fan-out can erase depth advantages once repeater insertion is accounted for (Held et al., 2015). In spin-wave systems, FO2 can be achieved with negligible amplitude mismatch, but not with net power gain (Mahmoud et al., 2021). In optical reformating, reciprocity ensures reverse fan-in operation, but the total loss remains identical in both directions (Thomson et al., 2012). In superconducting neuromorphic hardware, fan-out scales to human-brain-like levels, yet area, junction count, and path-equalization remain the controlling constraints (Schneider et al., 2020).

Taken together, these studies portray a fan-in/fan-out system as a physically instantiated distribution-and-aggregation architecture whose performance is set by a small set of recurrent variables: overlap fidelity, path symmetry, loading, crosstalk, routing complexity, and the cost of enforcing bounded fan-out. The implementation details differ sharply by platform, but the governing problem is structurally the same.