Energy Roofline Model Overview

• Energy Roofline Model is a framework that relates operational intensity to energy per operation and per byte to distinguish between compute-bound and memory-bound regimes.
• It integrates throughput and energy analyses through core equations, revealing distinct performance and energy knees that impact system design decisions.
• The model offers practical insights for designing and mapping workloads by leveraging design levers such as data reuse, bandwidth optimization, and efficient architectural choices.

The energy roofline model is a family of analytical models that extends the classical roofline by expressing not only attainable performance but also the energy or energy efficiency associated with computation and data movement. In its most direct form, it relates operational intensity to energy per operation, energy per byte, or energy efficiency, and it distinguishes compute-dominated from memory-dominated execution regimes. In recent work, the model has been specialized for hierarchical ML accelerators, distributed Transformer fine-tuning, HPC AI benchmarking, GPU DVFS, and edge accelerators, but the central objective remains the same: to expose which resource sets the governing bound, where the relevant “knee” lies, and how architecture, mapping, or operating-point choices move a workload relative to that bound (Verhelst et al., 22 May 2025, Ghane et al., 2018, K. et al., 24 Sep 2025).

1. Classical roofline antecedents and the energy extension

The classical roofline is defined by operational intensity and two ceilings: peak compute and peak memory bandwidth. With operational intensity $I = \frac{\mathrm{FLOPs}}{\mathrm{Bytes}}$, achieved performance is bounded by

$$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$

so low-intensity kernels are bandwidth-bound and sufficiently high-intensity kernels become compute-bound. This formulation remains the baseline in later energy-aware variants, even when the workload is expressed in ops rather than FLOPs or when communication traffic replaces memory traffic as the dominant transfer term (Verhelst et al., 22 May 2025, Jiang et al., 2020).

Energy roofline formulations retain the same balance-point logic but replace or augment the performance axis with energy-oriented quantities. One line of work formulates kernel-dependent energy as the sum of computation and memory-transfer terms,

$$E_C = W\,\epsilon_{\mathrm{flop}} + Q\,\epsilon_{\mathrm{mem}},$$

and then derives energy per FLOP, energy per byte, and performance-per-watt from the same variables. In that construction, the compute-oriented and memory-oriented plots use $E_{\mathrm{op}}$ and $E_{\mathrm{byte}}$ on the horizontal axis and power on the vertical axis, with slopes set by achieved compute performance or achieved bandwidth and a horizontal ceiling set by the peak observed or allowed power (Ghane et al., 2018).

A second line of development, especially in ML accelerator analysis, preserves the familiar throughput roofline and explicitly layers an energy roofline over it. There, throughput remains a minimum over ceilings, but energy per operation becomes a sum of contributions from compute and memory movement across the hierarchy. This difference in algebraic structure is consequential: throughput rooflines form sharp corners, whereas energy rooflines are smooth curves because multiple memory levels can contribute simultaneously (Verhelst et al., 22 May 2025).

2. Core equations, ceilings, and knees

In the enhanced ML-accelerator formulation, the central variable is operational intensity at a memory level $L$,

$\mathrm{OI}_L \equiv \frac{N_{\mathrm{op}}}{N_L},$

where $N_{\mathrm{op}}$ is the number of operations in a task and $N_L$ is the bytes moved at memory level $L$. A multiply-accumulate counts as $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$0 ops. For a single level, attainable throughput obeys

$$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$1

For ML accelerators with $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$2, the throughput roofline becomes

$$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$3

where $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$4 is clock frequency, $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$5 are per-level bandwidths in bytes/cycle, and $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$6 is the number of arithmetic operators available on chip. The limiting diagonal is the memory level with the smallest $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$7, while the flat ceiling is $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$8. The throughput knee for level $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$9 is

$$E_C = W\,\epsilon_{\mathrm{flop}} + Q\,\epsilon_{\mathrm{mem}},$$0

(Verhelst et al., 22 May 2025)

The corresponding energy model defines total task energy as

$$E_C = W\,\epsilon_{\mathrm{flop}} + Q\,\epsilon_{\mathrm{mem}},$$1

which yields energy per operation

$$E_C = W\,\epsilon_{\mathrm{flop}} + Q\,\epsilon_{\mathrm{mem}},$$2

and energy efficiency

$$E_C = W\,\epsilon_{\mathrm{flop}} + Q\,\epsilon_{\mathrm{mem}},$$3

At low $$E_C = W\,\epsilon_{\mathrm{flop}} + Q\,\epsilon_{\mathrm{mem}},$$4, memory energy dominates through the $$E_C = W\,\epsilon_{\mathrm{flop}} + Q\,\epsilon_{\mathrm{mem}},$$5 terms; at high $$E_C = W\,\epsilon_{\mathrm{flop}} + Q\,\epsilon_{\mathrm{mem}},$$6, compute energy dominates and $$E_C = W\,\epsilon_{\mathrm{flop}} + Q\,\epsilon_{\mathrm{mem}},$$7 approaches the compute-efficiency ceiling $$E_C = W\,\epsilon_{\mathrm{flop}} + Q\,\epsilon_{\mathrm{mem}},$$8. The energy knee for level $$E_C = W\,\epsilon_{\mathrm{flop}} + Q\,\epsilon_{\mathrm{mem}},$$9 occurs roughly at

$E_{\mathrm{op}}$0

A central result is that throughput knees and energy knees generally do not coincide, because one depends on bandwidth and the other on energy per byte. A workload can therefore be compute-bound for throughput while still being energy-bound by memory, or vice versa (Verhelst et al., 22 May 2025).

Related formulations in training and system-level studies use different variables but preserve the same separation. For distributed Transformer fine-tuning, arithmetic intensity is $E_{\mathrm{op}}$1, where $E_{\mathrm{op}}$2 is FLOPs and $E_{\mathrm{op}}$3 is memory traffic, and the lower bounds are

$E_{\mathrm{op}}$4

The same work also uses the additive model

$E_{\mathrm{op}}$5

and a reduced-form scaling law,

$E_{\mathrm{op}}$6

where $E_{\mathrm{op}}$7 is a speedup-derived hardware-efficiency factor for tensor parallelism and FSDP/DP (Mayaki, 22 Jun 2026).

3. Hierarchical operational intensity in ML accelerators

A distinctive feature of ML accelerators is that operational intensity is not a single number. Because dataflow and tiling create spatial and temporal reuse, $E_{\mathrm{op}}$8 differs across RF, SRAM, and DRAM. This is the main reason the enhanced roofline model in accelerator studies is hierarchical rather than single-level. Spatial reuse can duplicate inputs, weights, or outputs across a PE array dimension, while temporal stationarity holds one tensor stationary at a given level. Larger arrays, larger buffers, and better loop blocking all reduce reload factors and increase $E_{\mathrm{op}}$9 at the relevant level (Verhelst et al., 22 May 2025).

For convolution with batch $E_{\mathrm{byte}}$0, input channels $E_{\mathrm{byte}}$1, output channels $E_{\mathrm{byte}}$2, kernel $E_{\mathrm{byte}}$3, and output $E_{\mathrm{byte}}$4, the paper gives

$E_{\mathrm{byte}}$5

and models bytes moved at level $E_{\mathrm{byte}}$6 through reload factors $E_{\mathrm{byte}}$7,

$E_{\mathrm{byte}}$8

so that

$E_{\mathrm{byte}}$9

Weight-stationary reduces $L$0, output-stationary reduces $L$1, and input-stationary reduces $L$2. For GEMM or attention with $L$3, $L$4, and output $L$5,

$L$6

and a single-pass DRAM approximation is

$L$7

giving

$L$8

Systolic or $L$9-D/$\mathrm{OI}_L \equiv \frac{N_{\mathrm{op}}}{N_L},$0-D arrays can provide multi-dimensional spatial reuse, reducing per-cycle byte scaling and pushing $\mathrm{OI}_L \equiv \frac{N_{\mathrm{op}}}{N_L},$1 upward (Verhelst et al., 22 May 2025).

The paper’s illustrative $\mathrm{OI}_L \equiv \frac{N_{\mathrm{op}}}{N_L},$2 nm parameters make the hierarchy concrete: $\mathrm{OI}_L \equiv \frac{N_{\mathrm{op}}}{N_L},$3 pJ/op, $\mathrm{OI}_L \equiv \frac{N_{\mathrm{op}}}{N_L},$4 pJ/byte, $\mathrm{OI}_L \equiv \frac{N_{\mathrm{op}}}{N_L},$5 pJ/byte, $\mathrm{OI}_L \equiv \frac{N_{\mathrm{op}}}{N_L},$6 pJ/byte, with $\mathrm{OI}_L \equiv \frac{N_{\mathrm{op}}}{N_L},$7 B/cycle, $\mathrm{OI}_L \equiv \frac{N_{\mathrm{op}}}{N_L},$8 B/cycle, and $\mathrm{OI}_L \equiv \frac{N_{\mathrm{op}}}{N_L},$9 B/cycle. The resulting energy knees are $N_{\mathrm{op}}$0, $N_{\mathrm{op}}$1, and $N_{\mathrm{op}}$2 ops/byte for RF, SRAM, and DRAM. Under these numbers, compute-dominated energy behavior requires especially high $N_{\mathrm{op}}$3 at DRAM, which explains why accelerator design emphasizes reuse at upper memory levels rather than only improving raw arithmetic throughput (Verhelst et al., 22 May 2025).

4. System-specific variants and related formulations

In ML accelerators, the energy roofline is primarily a hierarchy-aware model of compute energy plus multi-level memory energy. In distributed Transformer fine-tuning, the model becomes a scaling law in which compute proxy, activation-volume proxy, and hardware efficiency jointly determine training energy. The fitted model

$N_{\mathrm{op}}$4

was estimated across $N_{\mathrm{op}}$5 configurations on a single $N_{\mathrm{op}}$6-GPU RTX 2080 Ti node, and dropping $N_{\mathrm{op}}$7 reduced adjusted $N_{\mathrm{op}}$8 from $N_{\mathrm{op}}$9 to approximately $N_L$0. This formulation shifts attention from kernel-local memory ceilings to multi-GPU efficiency degradation under tensor parallelism and FSDP/DP (Mayaki, 22 Jun 2026).

In HPC AI benchmarking, the dominant transfer term may be communication rather than memory traffic. HPC AI500 therefore defines communication operation intensity,

$N_L$1

where $N_L$2 is communication traffic among accelerators, and uses

$N_L$3

for single-node and distributed settings. The same framework introduces Valid FLOPS and Valid FLOPS per watt, thereby supplying the ingredients for a quality-aware energy roofline even though the paper does not explicitly present an energy-aware roofline figure (Jiang et al., 2020).

For GPUs, earlier work framed the energy roofline directly in power space. The compute plot uses

$N_L$4

and the memory plot uses

$N_L$5

with optimization ceilings corresponding to occupancy, FMA, ILP, and memory-access patterns. The empirical findings were architecture-sensitive: on GTX 970, increasing threads and blocks improved energy efficiency with only a small power increase for single precision, while on Tesla K80 ILP was the primary route to energy efficiency; on both GPUs, strided accesses sharply reduced memory energy efficiency (Ghane et al., 2018).

Edge and DVFS studies incorporate operating-point dependence into the roofline parameters themselves. On Jetson Orin AGX, total energy is modeled as

$N_L$6

with time roofline

$N_L$7

and the break-even energy intensity

$N_L$8

For MAXN, the reported empirical fits are $N_L$9 TFLOP/s, $L$0 GB/s, $L$1 pJ/FLOP, $L$2 pJ/byte, and $L$3 W, giving $L$4 FLOP/byte and $L$5 FLOP/byte. The same study reports that MAXN is not the most energy-efficient mode and that time efficiency implies energy efficiency for all power modes (K. et al., 24 Sep 2025).

A related DVFS formulation for Tesla V100 models power as

$L$6

runtime as

$L$7

and energy efficiency as $L$8. Under this “DVFS roofline phenomenon,” compute-bound kernels benefit from increasing $L$9 up to the memory-bound transition, while memory-bound kernels do not. The reported optimizer improved energy efficiency by approximately $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$00 while maintaining performance within a $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$01 loss margin (Wang et al., 2024).

5. Design levers, optimization workflow, and interpretive use

Across these variants, the principal design levers are reuse, bandwidth, compute efficiency, and utilization. In the hierarchical accelerator model, loop blocking and tiling reduce reload factors $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$02, dataflow selection chooses which tensor is stationary at each level, larger RF and SRAM sizes permit larger tiles, quantization reduces $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$03 and $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$04 while increasing ops per byte, operator fusion raises $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$05 at SRAM and DRAM, and near-/in-memory compute can both raise effective memory-bound slopes and lower memory energy. The same framework notes that sparsity and compression may reduce $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$06 and increase effective $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$07, but index overhead, indirection, and locality loss must be accounted for; unstructured sparsity can detach operating points from the roofline because bandwidth is underutilized (Verhelst et al., 22 May 2025).

The enhanced accelerator paper also gives an explicit procedure for applying the model to a new design: characterize hardware peaks $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$08, per-level bandwidths $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$09, and energy parameters $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$10; map representative layers to obtain per-level $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$11; place workloads on throughput and energy rooflines; identify the limiting regime; then iterate architecture and mapping while re-evaluating utilization. Effective throughput and energy efficiency are treated as roofline values multiplied by utilizations $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$12 and $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$13, which is why double-buffering, pipeline parallelism, and flexible dataflow are presented as necessary complements to formal ceilings (Verhelst et al., 22 May 2025).

Distributed training and DVFS-oriented work broaden the same optimization logic. In fine-tuning, the dominant lever may be the hardware-efficiency term $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$14, not just compute or memory proxy magnitudes; the measured result that a $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$15 improvement in $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$16 reduces energy by about $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$17–$$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$18 reflects that shift in emphasis (Mayaki, 22 Jun 2026). In DVFS settings, the practical rule is to avoid overscaling core frequency beyond the memory-bound transition. On Jetson Orin AGX, many common inference workloads are memory-bound, so maintaining memory frequency while reducing GPU frequency moderately can lower energy with minimal latency loss; on Tesla V100, the modeled optimum likewise occurs at the largest feasible core frequency that remains on the useful side of the compute-to-memory transition for the chosen memory frequency (K. et al., 24 Sep 2025, Wang et al., 2024).

6. Caveats, misconceptions, and open directions

A recurrent misconception is that reaching the compute-bound region in throughput implies energy-efficient execution. The enhanced ML-accelerator roofline explicitly rejects this equivalence: the throughput knee is $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$19, whereas the energy knee is $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$20, so the two transitions need not align. A workload can therefore be compute-bound for throughput while still paying dominant DRAM energy, and raising $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$21 can even move the throughput knee to the right, increasing memory pressure without improving energy efficiency at moderate $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$22 (Verhelst et al., 22 May 2025).

Another misconception is that roofline bounds are exact. Multiple studies note that ideal overlap assumptions, rounded transitions, bank conflicts, NoC contention, burst inefficiency, layout conversion overheads, irregular sparsity, and communication overheads push measured points below the roofline. In HPC AI500, communication ceilings and quality penalties are necessary because measured training behavior is often dominated by interconnect rather than device-local arithmetic. In LULESH on Intel Ice Lake and Sapphire Rapids, relevant energy savings were only possible for memory-bound functions by using fewer cores per ccNUMA domain and/or reducing the core clock speed, but the very high extrapolated baseline power on both chips made concurrency throttling less effective (Jiang et al., 2020, Afzal et al., 2024).

Open directions in the ML-accelerator survey include $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$23D integration and chiplets, near-/in-memory compute and IMC, analog compute and switched-capacitor IMC, DRAM-PIM and inclusive PIM, better compression and sparsity formats, and adaptive precision with DVFS. The survey’s stated rationale is that these directions can raise bandwidth ceilings, lower $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$24 or $$P = \min\!\left(P_{\mathrm{peak}},\, B \cdot I\right),$$25, or preserve locality while increasing operational intensity at the right levels. A plausible implication is that future energy roofline work will continue to move away from single-ceiling abstractions and toward models that couple hierarchy, utilization, communication, and operating mode in a unified description (Verhelst et al., 22 May 2025).