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EC-SpMV: Exact, Encrypted & Compressed Multiplication

Updated 6 July 2026
  • EC-SpMV is a family of sparse matrix–vector multiplication methods defined by varying arithmetic semantics, storage designs, and system objectives.
  • The approaches leverage techniques such as lazy modular reduction, explicitly cached GPU kernels, and compressed formats for exact, encrypted, and energy-conscious computations.
  • Applications range from black-box linear algebra and homomorphic encryption to efficient sparse LLM inference and energy-saving Boolean matrix operations.

EC-SpMV denotes several specialized forms of sparse matrix–vector multiplication centered on the kernel y=Axy = A x, but differentiated by arithmetic semantics, storage design, and systems objectives. In the cited literature, the label has been used for exact arithmetic over finite fields and modular rings, explicitly cached GPU kernels, ciphertext–ciphertext evaluation under homomorphic encryption, extraction-and-compression schemes for sparse LLM inference, and energy-conscious execution directly on losslessly compressed Boolean matrices (Boyer et al., 2010, Chen, 2022, Gao et al., 5 Mar 2026, Lin et al., 16 Jul 2025, Tosoni et al., 2024). The shared invariant is sparse linear application; the substantive differences lie in whether the principal constraint is exactness, memory traffic, communication, privacy, storage overhead, or energy.

1. Terminology and semantic range

In the cited literature, the label “EC-SpMV” appears in several distinct senses. The earliest cited use is the exact sparse matrix–vector multiplication of Dumas, Gautier, and Pernet, formulated over Fp\mathbb{F}_p and Z/mZ\mathbb{Z}/m\mathbb{Z} (Boyer et al., 2010). Later uses attach the same label to explicitly cached GPU kernels (Chen, 2022), encrypted ciphertext–ciphertext SpMV under BFV (Gao et al., 5 Mar 2026), sparse-LLM extraction-and-compression kernels (Lin et al., 16 Jul 2025), and energy-conscious SpMV over compressed Boolean-matrix formats (Tosoni et al., 2024).

Interpretation of EC-SpMV Computational setting Defining mechanisms
Exact sparse matrix–vector multiplication Finite fields and modular rings Lazy modular reduction, hybrid sparse formats, LinBox integration
Explicitly cached SpMV GPU memory hierarchy Shared-memory caching of xx, sliced ELL + ER, compact local indices
Encrypted ciphertext–ciphertext SpMV Homomorphic encryption CSSC format, chunked packing, rotations, masking
Extraction-and-compression SpMV Sparse LLM inference Hierarchical block extraction, EC-CSR, delta indexing
Energy-conscious compressed SpMV Boolean matrices, real vectors Zuckerli, k²-tree, mm-repair, direct execution on compressed data

This multiplicity is important because identical acronymal usage does not imply algorithmic equivalence. Exact EC-SpMV is about modular correctness; encrypted EC-SpMV is about confidentiality; sparse-LLM EC-SpMV is about batch-size-1 GPU efficiency; and energy-conscious EC-SpMV is about space–time–energy trade-offs on compressed data.

2. Exact arithmetic EC-SpMV over finite fields and rings

Exact EC-SpMV computes sparse matrix–dense vector products in exact arithmetic rather than in floating point. For A(Z/mZ)n×nA \in (\mathbb{Z}/m\mathbb{Z})^{n \times n} or AFpn×nA \in \mathbb{F}_p^{n \times n} and xx in the corresponding vector space, the output is y=Axmodmy = A x \bmod m or y=Axmodpy = A x \bmod p, with

yi=jN(i)Aijxjmodm,y_i = \sum_{j \in N(i)} A_{ij} x_j \bmod m,

where Fp\mathbb{F}_p0. The motivation is black-box linear algebra: exact arithmetic avoids rounding and cancellation, which is essential for rank and minimal-polynomial computations (Boyer et al., 2010).

The implementation space is organized around sparse formats and delayed modular reduction. COO exposes element-wise parallelism but, on GPUs, requires many reductions and often performs poorly because of atomics and divergence. CSR offers row-level parallelism and delayed reduction. ELL and ELLR are effective when row lengths are uniform; on CPUs, row-major ELL exploits cache locality, while on GPUs, column-major ELL yields coalesced memory access. Hybrid layouts such as ELL(R)+CSR and ELL(R)+COO are used for robust GPU performance, and the paper also introduces a custom COO′ format that is essentially CSR restricted to nonempty rows. Modular arithmetic is optimized through lazy reduction: if the accumulator supports magnitude up to Fp\mathbb{F}_p1, one can safely perform up to

Fp\mathbb{F}_p2

multiply-adds before reduction. Using symmetric representatives doubles the safe accumulation window, at the cost of a slightly more expensive final correction step.

A further optimization is the Fp\mathbb{F}_p3 specialization. When many entries are equal to Fp\mathbb{F}_p4, submatrices of Fp\mathbb{F}_p5 can replace multiplications with additions and subtractions and can eliminate value storage. The reported gains are up to roughly Fp\mathbb{F}_p6 on matrices of all ones and about Fp\mathbb{F}_p7 when about Fp\mathbb{F}_p8 of entries are Fp\mathbb{F}_p9. GPU kernels map one row, or a chunk of a long row, to one thread or warp; accumulators are kept in registers; and performance improves substantially when Z/mZ\mathbb{Z}/m\mathbb{Z}0, Z/mZ\mathbb{Z}/m\mathbb{Z}1, and Z/mZ\mathbb{Z}/m\mathbb{Z}2 remain resident on the device across iterations rather than being transferred at every SpMV.

The exact EC-SpMV library was integrated into LinBox, where it accelerated black-box methods such as block Wiedemann. In the sequence-generation phase, one computes

Z/mZ\mathbb{Z}/m\mathbb{Z}3

using repeated EC-SpMV on multi-vectors. The paper reports that sequence generation became faster than the native implementation, and the total runtime of parallel block Wiedemann rank computation on Z/mZ\mathbb{Z}/m\mathbb{Z}4 cores fell from Z/mZ\mathbb{Z}/m\mathbb{Z}5 to Z/mZ\mathbb{Z}/m\mathbb{Z}6 on EX5; for the same matrix, the sequence step dropped from Z/mZ\mathbb{Z}/m\mathbb{Z}7 to Z/mZ\mathbb{Z}/m\mathbb{Z}8. On the polynomial side, OpenMP-parallel polynomial matrix multiplication reached up to about Z/mZ\mathbb{Z}/m\mathbb{Z}9 speedup on xx0 cores, while the parallel sigma-basis PM-Basis achieved up to about xx1 speedup. The principal edge cases remained irregular sparsity, padding overhead in ELL, load imbalance in CSR, and overflow management for very small or very large moduli.

3. Communication locality and memory-hierarchy specialization

Related work pursued analogous goals through topology-aware communication, explicit caching, and architecture-specific sparse formats, even when the acronym itself changed. NAPSpMV reduces expensive inter-node communication by aggregating vector entries at the node level and replacing many rank-to-rank messages with fewer node-pair exchanges; EHYB explicitly caches tiles of the input vector in GPU shared memory; and ECM-guided tuning on A64FX replaces CRS with SELL-C-xx2 to approach bandwidth saturation (Bienz et al., 2016, Chen, 2022, Alappat et al., 2021).

In NAPSpMV, the matrix is partitioned across MPI ranks, then off-process dependencies are refined into on-node and off-node components. The communication pattern is reorganized into intra-node gather, inter-node send/receive, and intra-node scatter. The time model distinguishes

xx3

and the motivation is that intra-node messages are cheaper than inter-node injections. On Blue Waters, the method scaled to xx4 MPI processes and improved performance over the reference by up to two orders of magnitude on random matrices, with especially strong gains on coarse AMG levels where standard SpMV injects many small messages.

EHYB targets a different bottleneck: repeated global-memory fetches of irregularly indexed xx5 on GPUs. It partitions the matrix into a sliced ELL part and an extra-rows part. Each CUDA block loads a contiguous tile of xx6 into shared memory, and indices in the cached sliced-ELL part are stored as xx7-bit partition-local offsets. This reduces column-index traffic and amortizes xx8 loads across many references. On an NVIDIA Tesla V100, EHYB outperformed holaSpMV, CSR5, merge-based CSR, and cuSPARSE in both single and double precision; against cuSPARSE generic SpMV ALG2, the reported average speedup was xx9 in single precision and A(Z/mZ)n×nA \in (\mathbb{Z}/m\mathbb{Z})^{n \times n}0 in double precision.

On A64FX, the central result is that CRS is not a good practical choice because short inner loops, gather latency, and reduction overhead waste the bandwidth available from the HBM2-backed Core Memory Groups. The ECM model identifies partial overlap at L1 and full overlap at the L2/memory interface, and the optimization path is SELL-C-A(Z/mZ)n×nA \in (\mathbb{Z}/m\mathbb{Z})^{n \times n}1 with SVE intrinsics, padding, and column-wise accumulation across chunk height A(Z/mZ)n×nA \in (\mathbb{Z}/m\mathbb{Z})^{n \times n}2. With A(Z/mZ)n×nA \in (\mathbb{Z}/m\mathbb{Z})^{n \times n}3, SELL-16-1 saturated CMG bandwidth at about A(Z/mZ)n×nA \in (\mathbb{Z}/m\mathbb{Z})^{n \times n}4 cores, whereas SELL-8-1 saturated at A(Z/mZ)n×nA \in (\mathbb{Z}/m\mathbb{Z})^{n \times n}5 cores. The same study also explored system-level tuning on Fugaku and reported median energy savings of about A(Z/mZ)n×nA \in (\mathbb{Z}/m\mathbb{Z})^{n \times n}6 for SpMV using eco mode and frequency reduction. These results do not redefine EC-SpMV as a single scheme; they show that sparse matrix–vector multiplication is repeatedly reformulated around the dominant locality bottleneck of the target platform.

4. Encrypted EC-SpMV under homomorphic encryption

In the encrypted interpretation, EC-SpMV is ciphertext–ciphertext sparse matrix–vector multiplication carried out under homomorphic encryption. The target operation is again A(Z/mZ)n×nA \in (\mathbb{Z}/m\mathbb{Z})^{n \times n}7 with

A(Z/mZ)n×nA \in (\mathbb{Z}/m\mathbb{Z})^{n \times n}8

but now both operands remain encrypted throughout evaluation. The implementation uses a three-party model: Client A owns the sparse matrix, Client B owns the dense vector, and a semi-honest cloud server performs the homomorphic evaluation. Client A shares only plaintext column-index metadata with Client B to reorganize the vector, while the cloud does not learn nonzero locations or row or column indices (Gao et al., 5 Mar 2026).

The core structural contribution is CSSC, “Compressed Sparse Sorted Column.” For a sparse matrix A(Z/mZ)n×nA \in (\mathbb{Z}/m\mathbb{Z})^{n \times n}9, CSSC is

AFpn×nA \in \mathbb{F}_p^{n \times n}0

where VA stores nonzero values of the left-aligned matrix in column-major order, CI stores original column indices, RM is the row permutation after sorting rows by descending nnz, and CP is a column-pointer prefix-sum array. The format is designed for HE rather than for classical CSR/CSC traversal: rows are sorted by nnz, nonzeros are left-aligned within each row, and the matrix is flattened column-by-column so that ciphertext slots align deterministically with reorganized vector slots. A chunked packing scheme ensures that each chunk fits within one ciphertext.

The HE layer uses BFV with ring degree AFpn×nA \in \mathbb{F}_p^{n \times n}1, plaintext modulus AFpn×nA \in \mathbb{F}_p^{n \times n}2, coefficient-modulus chain AFpn×nA \in \mathbb{F}_p^{n \times n}3, and AFpn×nA \in \mathbb{F}_p^{n \times n}4-bit security. One ciphertext–ciphertext multiplication is performed per chunk, followed by a fixed-depth aggregation phase consisting of rotations, additions, and one ciphertext–plaintext masking multiplication per chunk. The operation counts are explicit: for AFpn×nA \in \mathbb{F}_p^{n \times n}5 chunks and AFpn×nA \in \mathbb{F}_p^{n \times n}6 the maximum chunk width, Step 1 uses AFpn×nA \in \mathbb{F}_p^{n \times n}7 HE-Mult operations; Step 2 uses AFpn×nA \in \mathbb{F}_p^{n \times n}8 HE-CMult operations, AFpn×nA \in \mathbb{F}_p^{n \times n}9 HE-Rot operations, and xx0 HE-Add operations. The total multiplicative depth is “xx1,” so no bootstrapping is required.

The reported experimental profile emphasizes both runtime and memory reduction relative to prior HE baselines. Average runtime improvements exceed xx2, with peaks above xx3; for example, on p2p-Gnutella31 the method ran in xx4 against baselines ranging from xx5 to more than xx6 days. Memory savings range from about xx7 to xx8 in the examples summarized in the paper. The method is nevertheless not fully structure-hiding: CI metadata is revealed to Client B, which means column-wise sparsity structure may leak to that party. The design also assumes static sparsity, shallow arithmetic depth, and chunk sizes that remain compatible with the slot capacity of the BFV parameter set.

5. EC-SpMV for sparse LLM inference

In sparse LLM inference, EC-SpMV refers to an extraction-and-compression SpMV scheme specialized for the decoder phase at batch size xx9. In that regime, dense GEMMs degenerate to GEMV, and after unstructured pruning they become SpMV. The problem is not extreme sparsity in the classical scientific-computing sense; it is moderate sparsity with substantial per-element indexing overhead and semi-regular local structure. The proposed response is a co-design of hierarchical block extraction and a compressed sparse format called EC-CSR (Lin et al., 16 Jul 2025).

The block-extraction algorithm identifies multi-granularity blocks by repeatedly matching rows with overlapping column sets, first forming as many y=Axmodmy = A x \bmod m0-row blocks as possible, then aggregating them into y=Axmodmy = A x \bmod m1-row, y=Axmodmy = A x \bmod m2-row, and coarser structures through a meta-matrix representation. If a nonzero belongs to a block of granularity y=Axmodmy = A x \bmod m3, the amortized cost of loading one y=Axmodmy = A x \bmod m4 element is reduced from y=Axmodmy = A x \bmod m5 to y=Axmodmy = A x \bmod m6. The paper writes the total input-vector access cost as

y=Axmodmy = A x \bmod m7

so the design objective is to maximize y=Axmodmy = A x \bmod m8 wherever possible. After extraction, the algorithm applies block clipping and reordering for load balance.

EC-CSR stores each block set using row indices, block pointers, base indices, delta indices, block values, and set metadata. Given sorted column indices y=Axmodmy = A x \bmod m9, the format stores a base index y=Axmodpy = A x \bmod p0 and deltas y=Axmodpy = A x \bmod p1, reconstructing

y=Axmodpy = A x \bmod p2

This permits low-precision delta storage because adjacent columns in sparse LLM weights often differ by small strides. The paper reports that for LLaMA weights pruned to y=Axmodpy = A x \bmod p3, y=Axmodpy = A x \bmod p4, and y=Axmodpy = A x \bmod p5 sparsity, most deltas are below y=Axmodpy = A x \bmod p6, y=Axmodpy = A x \bmod p7, and y=Axmodpy = A x \bmod p8, respectively, which enables uint8 delta encoding at those sparsity levels.

The GPU kernel maps one warp to one block. Each warp splits block columns into warp-size sub-blocks, streams vectorized delta-index and value segments, keeps per-row accumulators in registers, and uses warp-level reduction before atomic accumulation into the output rows. On real sparse weight matrices from LLaMA and OPT models, EC-SpMV achieved up to y=Axmodpy = A x \bmod p9 speedup over state-of-the-art SpMV libraries and reduced storage overhead by up to yi=jN(i)Aijxjmodm,y_i = \sum_{j \in N(i)} A_{ij} x_j \bmod m,0 compared with CSR. The end-to-end decoder case study in llama.cpp for LLaMA2-7B at yi=jN(i)Aijxjmodm,y_i = \sum_{j \in N(i)} A_{ij} x_j \bmod m,1 sparsity on an RTX 3090 reported yi=jN(i)Aijxjmodm,y_i = \sum_{j \in N(i)} A_{ij} x_j \bmod m,2, yi=jN(i)Aijxjmodm,y_i = \sum_{j \in N(i)} A_{ij} x_j \bmod m,3, and yi=jN(i)Aijxjmodm,y_i = \sum_{j \in N(i)} A_{ij} x_j \bmod m,4 tokens/s at generation lengths yi=jN(i)Aijxjmodm,y_i = \sum_{j \in N(i)} A_{ij} x_j \bmod m,5, yi=jN(i)Aijxjmodm,y_i = \sum_{j \in N(i)} A_{ij} x_j \bmod m,6, and yi=jN(i)Aijxjmodm,y_i = \sum_{j \in N(i)} A_{ij} x_j \bmod m,7, versus yi=jN(i)Aijxjmodm,y_i = \sum_{j \in N(i)} A_{ij} x_j \bmod m,8, yi=jN(i)Aijxjmodm,y_i = \sum_{j \in N(i)} A_{ij} x_j \bmod m,9, and Fp\mathbb{F}_p00 tokens/s for the dense baseline; memory footprint fell from Fp\mathbb{F}_p01 GB in dense form and Fp\mathbb{F}_p02 GB in CSR-32 to Fp\mathbb{F}_p03 GB in EC-CSR. The stated scope remains batch-size-Fp\mathbb{F}_p04, static sparsity, and single-GPU execution; for higher batch sizes, dense or block-sparse GEMM may again dominate.

A further meaning of EC-SpMV is explicitly “energy-conscious, lossless compressed sparse matrix–vector multiplication performed directly on compressed formats, without prior decompression.” Here the matrices are Boolean, vectors are real-valued, and the right product is

Fp\mathbb{F}_p05

The paper evaluates Zuckerli, k²-tree, and grammar-compressed mm-repair representations on server and edge platforms, measuring execution time, compression ratio, and energy rather than only throughput (Tosoni et al., 2024).

The three formats embody different trade-offs. Zuckerli is usually the most succinct among the computation-friendly formats, reaching Fp\mathbb{F}_p06 bits per edge on indochina-2004 and about Fp\mathbb{F}_p07 BPE on uk-2005 and arabic-2005. k²-tree is less succinct but often faster than Zuckerli in single-thread runs. Grammar-based mm-repair variants are generally the fastest, with Re32 at the high-performance end and Reans reducing storage relative to other grammar encodings. The principal systems result is that selecting the right compressed format yields Fp\mathbb{F}_p08–Fp\mathbb{F}_p09 orders-of-magnitude energy savings across datasets and both platforms. A second result is that time-optimal and energy-optimal thread counts diverge: runtime may continue improving up to Fp\mathbb{F}_p10–Fp\mathbb{F}_p11 threads on the server, while energy often stops decreasing at Fp\mathbb{F}_p12–Fp\mathbb{F}_p13 threads; on Raspberry Pi, using Fp\mathbb{F}_p14 threads on a Fp\mathbb{F}_p15-core device can increase both time and energy. A common misconception is therefore that faster execution automatically minimizes energy; the reported measurements contradict that assumption.

A related, but terminologically distinct, line studies multiple-precision SpMV as a remedy for round-off sensitivity in Krylov methods (Kouya, 2024). That work does not redefine the acronym EC-SpMV, but it is relevant to the broader question of specialized sparse matrix–vector products under nonstandard numerical constraints. Using AVX2 SIMD, OpenMP, and multi-component DD, TD, QD, and MPFR arithmetic, it reports speedups up to Fp\mathbb{F}_p16 for real SpMV and Fp\mathbb{F}_p17 for complex SpMV on Fp\mathbb{F}_p18 threads in the mixed-precision setting. The numerical motivation differs from exact modular arithmetic: the goal is not residue-class exactness, but stabilization of convergence by reducing round-off errors. This suggests that the broader EC-SpMV landscape is best understood not as a single algorithmic lineage, but as a recurrent pattern in which the sparse matrix–vector product is re-engineered around the dominant correctness or efficiency constraint of a given domain.

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