DRAM-Access Reduction Frustum Culling

• The paper introduces a DRAM-access reduction strategy that restructures frustum culling to minimize off-chip memory traffic in 3D Gaussian Splatting.
• It reorganizes high-dimensional Gaussian data into coarse spatial-temporal cells, fetching full records only for cells intersecting the view frustum, cutting DRAM accesses by 70–75%.
• The approach, integrated into an algorithm–hardware co-design, enables sustained high FPS and lower power consumption on edge devices by minimizing costly memory operations.

Searching arXiv for the specified paper and closely related work to ground the article in current literature. DRAM-access reduction frustum culling is an algorithmic optimization for static and dynamic 3D Gaussian Splatting (3DGS) that reduces off-chip memory traffic during the first preprocessing stage of rendering by culling coarse spatial–temporal cells before fetching full Gaussian records from DRAM. In 3DGauCIM, the method is introduced as part of an algorithm–hardware co-design for high-frame-rate real-time edge rendering, where frustum culling, sorting, grouping, and rasterization must operate under narrow memory bandwidth, limited on-chip storage, and stringent power budgets (Huang et al., 25 Jul 2025).

1. Role in the 3DGS rendering pipeline

In both static and dynamic 3DGS, frustum culling is the first preprocessing step: the renderer must determine which Gaussian primitives lie within the camera’s view frustum before depth sorting, grouping, and rasterization proceed. The conventional approach fetches all Gaussian parameters from off-chip DRAM into the accelerator, tests each Gaussian against the six planes of the view frustum, and discards those outside. The transferred parameters include mean, covariance, color, opacity, and, in dynamic scenes, temporal mean and expanded covariance (Huang et al., 25 Jul 2025).

The motivation for DRAM-access reduction frustum culling arises from the cost of this conventional workflow on edge devices. Repeatedly transferring tens of millions of Gaussians dominates both latency and DRAM energy, particularly in dynamic scenes with expanded per-primitive parameterization. Profiling showed that the naïve frustum-culling stage alone can account for over 50% of the end-to-end rendering time. Within 3DGauCIM, DRAM-access reduction frustum culling is therefore positioned not as a peripheral optimization but as the entry point for reducing work and memory pressure throughout the downstream pipeline.

2. Problem statement and design objective

The central problem is that conventional frustum culling performs visibility testing only after every Gaussian has already been fetched into the accelerator. This makes visibility rejection expensive in exactly the regime where visibility rejection should save work. On edge devices with tight energy budgets and narrow memory bandwidth, the mismatch is particularly severe because out-of-view Gaussians still incur DRAM traffic before being discarded (Huang et al., 25 Jul 2025).

DRAM-access reduction frustum culling addresses this by reorganizing the Gaussian set offline into coarse spatial–temporal cells and performing runtime culling at the cell level rather than at the individual-Gaussian level. Only the identifiers of visible cells are needed on-chip during culling, together with their DRAM address ranges. Full Gaussian records remain off-chip and are fetched only for cells whose temporal and spatial extents intersect the current view configuration. This shifts the unit of early rejection from the Gaussian primitive to the cell.

A common misconception is that frustum culling in 3DGS necessarily requires immediate access to all per-Gaussian attributes. The method described here rejects that assumption: cell-vs-frustum testing uses only pre-known cell bounds and temporal bin limits, so no DRAM access is needed for cells outside the frustum. The design objective is therefore not to change the semantics of frustum culling, but to change when DRAM reads occur.

3. Offline 4D partitioning and data organization

The method partitions the entire 4D Gaussian set in two stages, offline, producing for each primitive a single “home” grid cell plus lightweight pointers in neighboring cells if the primitive’s spatial or temporal covariance crosses a boundary. Stage 1 subdivides the time axis into $N_T$ contiguous 1D bins according to each Gaussian’s temporal mean $\mu_t$. Stage 2 subdivides, within each time bin, the 3D volume into a uniform grid of $N_X \times N_Y \times N_Z$ cubic cells based on the spatial mean $\mathbf{\mu}_{xyz}$ (Huang et al., 25 Jul 2025).

The resulting storage rule is explicit. Every Gaussian’s full parameter record resides in exactly one “central” cell. Any neighboring cell that the Gaussian overlaps stores only a fixed-size pointer to that central record. When a Gaussian spans multiple cells because of large covariance, the full record is not duplicated across those cells; only the pointer is replicated.

This organization has two immediate consequences. First, each cell corresponds to a contiguous DRAM region, which supports burst-oriented access. Second, multi-cell overlap is encoded through indirection rather than record replication. The scheme is therefore designed to preserve contiguity for primary storage while avoiding redundant full-record placement for broad-support Gaussians.

4. Runtime frustum-cell culling and duplicate suppression

At each frame, given the camera pose $(E, K)$ and time $t$, runtime culling proceeds in two steps. The system first determines the visible set of temporal bins whose $t$-ranges overlap the frustum’s near–far interval $[z_{\min}, z_{\max}]$. It then determines, for each visible temporal bin, which of its spatial cubic cells intersect the view frustum through a standard cell-vs-frustum test using the cell bounds already known on-chip (Huang et al., 25 Jul 2025).

Only the identifiers of visible spatial–temporal cells are retained on-chip. Their associated DRAM address ranges, represented by start–end pointers, are streamed to the DRAM controller. When the runtime culler visits a cell, it fetches the cell’s contiguous block of full Gaussian records together with any pointers stored in that cell. A deduplication check in the on-chip controller suppresses duplicate pointer-triggered fetches if the corresponding central record has already been read.

The treatment of overlapping Gaussians is therefore operationally simple: store the entire Gaussian once, reference it elsewhere by pointer, and guard against repeated fetches with a small duplicate-suppression structure. This suggests that the method separates spatial–temporal overlap management from bulk record transport, allowing the fetch logic to remain compatible with contiguous cell-based DRAM access.

5. Mathematical formulation and access-count reduction

For coarse-cell testing, let the $i$-th frustum plane be

$\mathbf{n}_i \cdot \mathbf{x} + d_i = 0,$

where $\mu_t$0 is the outward normal and $\mu_t$1 is the plane offset. A cell with axis-aligned bounding box

$\mu_t$2

is outside the frustum if it lies fully on the negative side of any plane, namely if for some $\mu_t$3,

$\mu_t$4

An equivalent bounding-sphere approximation is also given: if the cell center is $\mu_t$5 and its radius is $\mu_t$6, then the cell is outside plane $\mu_t$7 if

$\mu_t$8

A cell that passes all six plane tests is inside or intersects the frustum (Huang et al., 25 Jul 2025).

The Gaussian fetch criterion is defined over visible cells. Let

$\mu_t$9

Runtime DRAM reads are issued over

$N_X \times N_Y \times N_Z$0

with duplicates removed. In the conventional approach, frustum culling requires one DRAM read per Gaussian, giving $N_X \times N_Y \times N_Z$1 reads. In DR-FC, the total reads are approximately $N_X \times N_Y \times N_Z$2, where $N_X \times N_Y \times N_Z$3 is the number of visible cells and $N_X \times N_Y \times N_Z$4 is the number of Gaussians in cell $N_X \times N_Y \times N_Z$5. Since typically $N_X \times N_Y \times N_Z$6, the reduction factor is

$N_X \times N_Y \times N_Z$7

Figure 1 reports the measured DRAM-access reduction factor as grid resolution increases on dynamic real-world scenes:

Grid size	Reduction factor
$N_X \times N_Y \times N_Z$8	2.94×
$N_X \times N_Y \times N_Z$9	3.03×
$\mathbf{\mu}_{xyz}$0	3.66×

In absolute terms, the method cuts the frustum-culling DRAM reads by roughly 70–75%. The reported trend indicates that finer 4D partitioning improves culling selectivity, although the data provided here do not quantify the corresponding metadata-management trade-off.

6. Memory hierarchy, hardware realization, and pipeline effects

The on-chip and off-chip data split is explicit. On-chip storage contains the cell bounding extents for every spatial–temporal cell, the DRAM pointer table $\mathbf{\mu}_{xyz}$1, and a small hash or bitmask per fetched Gaussian for duplicate suppression. Off-chip DRAM stores the full Gaussian parameter records, laid out so that each cell’s Gaussians occupy contiguous memory and thus maximize burst efficiency (Huang et al., 25 Jul 2025).

The hardware support includes a DR-FC controller implemented as a finite state machine that, for each frame, culls cells, outputs a sorted list of DRAM address ranges, and gates the DRAM interface so that burst reads are issued only for those ranges. The on-chip SRAM partition allocates a dedicated small SRAM, for example 64–256 KB, for the cell pointer table, while duplicate suppression is handled by a one-bit-per-Gaussian bitmask or a tiny CAM. The extra SRAM footprint remains below a few hundred kilobytes.

Within the overall 3DGauCIM pipeline, DR-FC is the first stage in the preprocessing kernel. After visible Gaussians are fetched, Adaptive Interval Initialization Bucket-Bitonic Sort produces depth-sorted buckets, Adaptive Tile Grouping clusters screen tiles based on Gaussian overlap to maximize on-chip buffer reuse at blending time, and rasterization and blending proceed via the DCIM-friendly dataflow. Because DR-FC reduces the number of primitives entering sorting and grouping, it also lowers work and memory pressure in those stages. This suggests that its effect is not confined to culling latency alone, but extends to the balance of the full preprocessing and rendering pipeline.

7. Performance significance and interpretive context

The reported performance significance of DRAM-access reduction frustum culling is tied to both isolated preprocessing savings and system-level edge-rendering results. In the culling stage itself, the method delivers a measured reduction that rises from 2.94× to 3.66× as the grid increases from $\mathbf{\mu}_{xyz}$2 to $\mathbf{\mu}_{xyz}$3. In system terms, when combined with the other algorithmic and DCIM-based optimizations of 3DGauCIM, the architecture sustains over 200 FPS in both static and dynamic large-scale real-world scenes, with 0.28 W for static scenes and 0.63 W for dynamic scenes. The same summary reports comparison to prior GSCore hardware at only $\mathbf{\mu}_{xyz}$4 FPS and 0.87 W (Huang et al., 25 Jul 2025).

The main significance of DR-FC is therefore architectural rather than merely procedural. It converts frustum culling from a stage dominated by per-Gaussian DRAM fetches into a stage dominated by on-chip metadata inspection and selective cell-based bursts. A plausible implication is that the method is especially relevant when scene scale and temporal parameterization make off-chip bandwidth the primary bottleneck. Another plausible implication is that the technique is most naturally paired with pipelines that can preserve cell contiguity in DRAM and can absorb modest metadata overhead on-chip.

The method should not be confused with an attempt to eliminate frustum culling or to replace Gaussian-level rendering semantics. Its specific contribution is to restructure visibility preprocessing so that the majority of out-of-view Gaussians are never fetched in the first place. In the context of static and dynamic 3DGS on resource-constrained edge devices, that restructuring is the essential contribution of DRAM-access reduction frustum culling.