Digit-Serial Modulo Arithmetic

• Digit-serial modulo arithmetic is a computational method that decomposes operands into fixed-size digits, enabling localized modular reduction without full-word carry propagation.
• It underpins efficient hardware architectures such as pipelined NTT accelerators, achieving improvements in speed, area savings, and reduced power consumption.
• The approach also utilizes split-channel arithmetic to balance wide moduli into narrower channels, simplifying local processing while preserving dynamic range.

to=arxiv_search 天天中彩票和json {"query":"digit-serial modulo arithmetic modular arithmetic NTT carryless arithmetic residue channels", "max_results": 10} Digit-serial modulo arithmetic denotes forms of modular computation in which operands are decomposed into small digits or narrow residue components and processed locally rather than as single full-width words. In one hardware realization, a $W$-bit operand is split into $W/d$ digits of $d$ bits and processed one digit per cycle through a pipelined datapath (Alexakis et al., 16 Jul 2025). In a complementary algebraic formulation, each digit position is treated as an independent residue, so addition becomes per-digit modular reduction and multiplication becomes coefficient convolution with local modular reduction and no carry propagation (Applegate et al., 2010). Specialized modulus families further extend the idea by replacing a wide residue channel, such as modulo $(2^{2n}+1)$, with multiple narrower channels whose arithmetic is locally simpler (Jaberipur et al., 2024). A broader, representation-oriented line of work uses banks of residues modulo many small moduli and CRT-based reconstruction, illustrating how distributed modular channels can encode integer structure even when the objective is not arithmetic hardware (Nakasho, 5 Mar 2026).

1. Core meaning and formal scope

A hardware-centric definition appears in pipelined NTT acceleration, where digit-serial operation means that the design “operates on digits with size $d$ bits effectively splitting the initial words into $W/d$ digits.” If $x$ is a $W$-bit operand, the implied digit decomposition is

$$x=\sum_{\ell=0}^{W/d-1} x_\ell 2^{\ell d}, \qquad 0\le x_\ell < 2^d.$$

The input coefficients arrive digit by digit; butterfly arithmetic is implemented by digit-serial adders and subtractors; the multiplier consumes and emits values in the same digit-stream format; and the next operator directly accepts that stream without reconstructing a full $W$-bit word (Alexakis et al., 16 Jul 2025).

An algebraic definition appears in carryless decimal arithmetic. If

$W/d$0

with digits $W/d$1, then carryless addition is

$W/d$2

and carryless multiplication is

$W/d$3

The first law is local digitwise modular reduction; the second is digit convolution followed by local coefficient reduction, with no carry chain between neighboring positions (Applegate et al., 2010).

These two formulations are not identical, but they share a common structural principle: arithmetic is organized around local modular processing on digits or channels, and long full-word carry propagation is avoided. This suggests that digit-serial modulo arithmetic is best understood as a family of modular-processing disciplines rather than a single algorithm.

2. Carry-free digitwise arithmetic as an algebraic model

Carryless decimal arithmetic provides a mathematically exact model of digitwise modular processing. The decisive formalization identifies a decimal string

$W/d$4

with the polynomial

$W/d$5

in

$W/d$6

Under this correspondence,

$W/d$7

where coefficient arithmetic is performed in $W/d$8. Equivalently,

$W/d$9

The interpretation explains why the operations are commutative, associative, and distributive, and it supplies a precise subtraction rule through digitwise $d$0-complements. For example, the negative of $d$1 is $d$2, and

$d$3

The same framework exposes the Chinese remainder decomposition

$d$4

which extends coefficientwise to

$d$5

Conceptually, carryless decimal arithmetic therefore splits into two independent digit-serial systems, one mod $d$6 and one mod $d$7, recombined by CRT (Applegate et al., 2010).

The model also shows how local modular processing changes the algebra. The units are only

$d$8

There are many zero divisors, including

$d$9

The zero divisors are exactly the “evenish” numbers, whose digits are all even, and the “fiveish” numbers, whose digits are all $(2^{2n}+1)$0 or $(2^{2n}+1)$1. Irreducibility rather than ordinary primality becomes the meaningful factorization notion. The CRT decomposition classifies the irreducibles as those for which exactly one component is irreducible and the other is a unit. The first few carryless primes are

$(2^{2n}+1)$2

and the paper derives the $(2^{2n}+1)$3-digit counting formula

$(2^{2n}+1)$4

Within the present topic, the importance of these results is not the decimal numerology itself, but the fact that a purely local digitwise rule admits a complete ring-theoretic treatment.

3. Homogeneous digit-serial modulo arithmetic in pipelined NTTs

A full hardware realization appears in pipelined NTT accelerators for FHE. The target modulus is $(2^{2n}+1)$5, the coefficient width is

$(2^{2n}+1)$6

and the architecture processes one $(2^{2n}+1)$7-bit digit per cycle while preserving a pipelined streaming datapath. The defining feature is homogeneity: addition, subtraction, multiplication, buffering, and inter-stage transfers all use the same digit-serial format, so the design never has to reassemble a full $(2^{2n}+1)$8-bit word between operators merely to perform modular correction or reduction. In a multipath architecture, the design can be arranged so that

$(2^{2n}+1)$9

under a 256-bit/cycle interface budget, with an example configuration of 8 paths $d$0 32-bit digits (Alexakis et al., 16 Jul 2025).

The arithmetic core is the radix-2 butterfly

$d$1

written in the stage form

$d$2

The method is built on Montgomery arithmetic. For radix $d$3, with $d$4, the Montgomery form is

$d$5

and Montgomery reduction is

$d$6

If the operands and twiddle are already in Montgomery form, then

$d$7

followed by Montgomery reduction to remain in Montgomery representation (Alexakis et al., 16 Jul 2025).

The key enabler of homogeneous streaming is redundant range representation: $d$8 The analysis shows that if all stage inputs lie in $d$9 and

$W/d$0

then the add-multiply output also lies in $W/d$1. For subtraction, the branch is aligned with the same range by replacing

$W/d$2

with

$W/d$3

which does not change the residue class modulo $W/d$4 but forces the representative into the range required by the common multiplier pipeline. The result is that no intermediate stage requires a final modular correction, so no inter-stage full-word normalization is needed (Alexakis et al., 16 Jul 2025).

The systolic digit-serial Montgomery multiplier contains $W/d$5 processing elements. Each PE is pipelined, each has single-cycle throughput and four-cycle latency, and each performs an effective shift by $W/d$6, so across $W/d$7 PEs the design realizes the total division by

$W/d$8

Stage buffers are digitized accordingly: a word-level stage buffer holding $W/d$9 words becomes

$x$0

entries of $x$1 bits each. The method therefore integrates arithmetic, timing, and storage around a single digit granularity.

4. Split-channel arithmetic for special moduli

A different but closely related line of work treats digit-seriality as width decomposition across residue channels. The motivating example is the modulus

$x$2

which augments the balanced RNS set

$x$3

but introduces a residue channel of about double the bit-width of the others. The proposed solution is to replace the single wide channel by two complex-valued $x$4-bit channels using

$x$5

The replacement therefore preserves both the dynamic range contribution of $x$6 and the coprimality structure required by the augmented moduli set (Jaberipur et al., 2024).

The conversion between the wide channel and the split channels is immediate. Writing

$x$7

one obtains

$x$8

The paper characterizes this mapping as “immediate and cost-free,” because it is achieved by reinterpretation of bit fields rather than by a substantive arithmetic network. Reverse conversion is similarly algebraic. For example, if

$x$9

then the corresponding modulo-$W$0 residue is

$W$1

An analogous formula holds for products (Jaberipur et al., 2024).

The adder and multiplier are designed directly over the split channels. For addition, the output is again expressed in stored-borrow and stored-carry form,

$W$2

with intermediate sums

$W$3

and correction bits

$W$4

For multiplication, the reduced form is

$W$5

where

$W$6

The importance of these formulas for digit-serial thinking is that one difficult $W$7-bit modular datapath is replaced by two regular $W$8-bit channels plus 1-bit correction metadata.

5. Performance characteristics and design tradeoffs

The NTT accelerator work makes the hardware tradeoffs explicit. Smaller digits reduce combinational complexity per stage and shorten the critical path, but they increase the number of digits per operand, the number of PEs per multiplier, and buffer expansion by a factor of $W$9. Under equal bandwidth constraints, the architecture uses

$$x=\sum_{\ell=0}^{W/d-1} x_\ell 2^{\ell d}, \qquad 0\le x_\ell < 2^d.$$0

so the total execution time in cycles remains nearly constant as $$x=\sum_{\ell=0}^{W/d-1} x_\ell 2^{\ell d}, \qquad 0\le x_\ell < 2^d.$$1 changes. For $$x=\sum_{\ell=0}^{W/d-1} x_\ell 2^{\ell d}, \qquad 0\le x_\ell < 2^d.$$2 bits and NTT sizes from 128 to 1024 points, the reported bandwidth-matched configuration of 8 paths $$x=\sum_{\ell=0}^{W/d-1} x_\ell 2^{\ell d}, \qquad 0\le x_\ell < 2^d.$$3 32-bit digits reaches 600 MHz versus 400 MHz for the compared Proteus design, a 33% increase, with area savings of about 7.9% to 8.7% and power savings of about 25% to 36%. For a 1024-point NTT, reducing the digit size from 128 bits to 16 bits “nearly doubles the maximum clock frequency” while increasing area by about 33% (Alexakis et al., 16 Jul 2025).

The split-channel $$x=\sum_{\ell=0}^{W/d-1} x_\ell 2^{\ell d}, \qquad 0\le x_\ell < 2^d.$$4 work emphasizes a different tradeoff: width balance across channels. Augmenting the set $$x=\sum_{\ell=0}^{W/d-1} x_\ell 2^{\ell d}, \qquad 0\le x_\ell < 2^d.$$5 with $$x=\sum_{\ell=0}^{W/d-1} x_\ell 2^{\ell d}, \qquad 0\le x_\ell < 2^d.$$6 increases the dynamic range by around 70%, but the single wide residue channel is “counter-productive” for speed balance. Replacing it by $$x=\sum_{\ell=0}^{W/d-1} x_\ell 2^{\ell d}, \qquad 0\le x_\ell < 2^d.$$7 preserves the dynamic range while restoring narrow-channel regularity. On Spartan-7S100 FPGA, the proposed unified moduli-$$x=\sum_{\ell=0}^{W/d-1} x_\ell 2^{\ell d}, \qquad 0\le x_\ell < 2^d.$$8 adder and multiplier are synthesized with particular emphasis on $$x=\sum_{\ell=0}^{W/d-1} x_\ell 2^{\ell d}, \qquad 0\le x_\ell < 2^d.$$9, for which the 6-bit LUT structure is favorable. The experiments show that the moduli-$W$0 add and multiply operations are advantageous versus moduli-$W$1 in speed, cost, and energy measures and collectively better than those of modulo-$W$2. The same study also reports that, to cover all the 32-bit numbers, the power-of-two channel can be widened to 12 bits with no harm to the speed balance across the five moduli (Jaberipur et al., 2024).

Taken together, these results show two recurring design principles. First, digit size is a tunable variable trading off frequency, area, and buffering in a homogeneous pipeline. Second, difficult wide moduli can sometimes be replaced by multiple narrow channels whose local arithmetic is simpler and more balanced.

6. Adjacencies, misconceptions, and limits of the term

Digit-serial modulo arithmetic is not exhausted by hardware pipelines, but not every modular decomposition is a digit-serial arithmetic method in the engineering sense. Carryless arithmetic is highly relevant because it gives a rigorous algebraic model of per-digit modular processing without carry propagation, and its multiplication law is exactly coefficient convolution over a residue ring. At the same time, it does not discuss hardware architecture, pipelining, latency, area, timing, digit-serial circuit design, systolic convolution, or modular reduction algorithms in the engineering sense (Applegate et al., 2010).

A second nearby area is distributed modular representation in machine learning. IntSeqBERT represents each integer using a continuous log-scale magnitude embedding together with sin/cos modulo embeddings for 100 residues, namely moduli $W$3 through $W$4, fused by FiLM inside a dual-stream Transformer. Its CRT-based solver reconstructs candidate integers from predicted magnitude, sign, and residue distributions, and the analysis reports a strong negative correlation between NIG and Euler’s totient ratio,

$W$5

This work is directly relevant to modular decomposition, per-modulus processing, and CRT-based recombination, but it does not discuss digit-serial residue update formulas, carry-save or digit-recurrence circuits, latency/throughput/area models, or exact modular multiplication pipelines (Nakasho, 5 Mar 2026).

A common misconception is therefore to treat all modular channelizations as instances of the same idea. The sources support a sharper distinction. Carryless arithmetic is an algebraic foundation for local digitwise modular computation. Homogeneous digit-serial NTT design is a full hardware discipline in which arithmetic operators, buffers, and inter-stage transfers all share a common small-digit format. Split-channel arithmetic for $W$6 is a width-reduction technique that is highly suggestive for digit-sliced or pipelined implementation, even though the reported architecture is combinational rather than serial. This suggests that the subject spans algebra, arithmetic architecture, and residue decomposition, with the unifying feature being local modular processing on digits or channels rather than word-level normalization after every operation.