Crossbar-Constrained Mapping

• Crossbar-constrained mapping is a technique for partitioning computational graphs onto physical crossbar arrays while strictly adhering to size, fan-in, and fan-out constraints.
• Optimization methods such as ILP, genetic algorithms, and clustered pruning are used to minimize area, energy, and latency while maintaining computational accuracy.
• Device-aware calibration, co-design strategies, and post-mapping adaptations are employed to address hardware non-idealities and enhance fault tolerance.

A crossbar-constrained mapping is the process of assigning computational graphs—predominantly for neural, logical, or communication workloads—onto arrays of finite-sized crossbar hardware, explicitly respecting the resource, operational, and non-ideality constraints intrinsic to the crossbar architecture. This mapping is essential to achieve maximal computational efficiency, fault tolerance, area/energy scaling, and robustness against non-idealities for in-memory computing platforms, neuromorphic systems, crossbar-based DNN accelerators, and circuit fabrics in both classical and emerging domains (Liang et al., 2018, Kazemi et al., 2020, Zhang et al., 2019, Park et al., 12 Jan 2025, Pohl et al., 3 Mar 2025, Sun et al., 2023).

1. Crossbar Array Architectures and Mapping Constraints

Memristive, resistive, or capacitive crossbars implement computation by encoding weights, logic states, or switching elements at the junctions of an m×n 2D array. Each crossbar is subject to strict size, fan-in, and fan-out limits due to technology: for example, in neural accelerators, a “functional crossbar” may be a 12×4 array including DAC/ADC periphery, and is tiled to create a compute fabric (Liang et al., 2018). The mapping of high-dimensional matrices or graphs onto crossbars must partition tensors or boolean matrices into tiles such that each tile fits the crossbar’s maximal row (M) and column (N) bounds:

$$\begin{align*} \text{tile size: } &M_\text{tile} \leq M_\text{crossbar}, \ &N_\text{tile} \leq N_\text{crossbar} \end{align*}$$

The crossbar’s periphery (DAC/ADC width, buffer depth, router bandwidth) further constrains operational utilization, quantization, and achievable throughput.

Beyond capacity, physical constraints include limits on per-line load (to prevent driver overload), maximum simultaneous device programming (to avoid sneak-path current), and in some contexts, explicit mapping conflicts (e.g., for on-chip network traffic or fault isolation) (Bhattacharjee et al., 2018, 0710.4671, Pohl et al., 3 Mar 2025). These constraints must be explicitly incorporated into the mapping algorithm or optimization problem to ensure correct, efficient, and reliable hardware execution.

2. Mathematical Formulations in Crossbar-Constrained Mapping

At its core, crossbar-constrained mapping is expressed as an optimization, typically combinatorial (ILP, MILP, or constrained gradient descent). The deployment assigns computational elements (weights, neurons, logic gates, traffic endpoints) to crossbar slots, subject to hardware constraints. Sample formulations include:

• Binary Assignment Variables:
  • $x_{i,j} \in \{0,1\}$: computational unit $i$ placed on crossbar $j$ (Pohl et al., 3 Mar 2025).
  • For mapping a DNN layer with weights $W \in \mathbb{R}^{m \times n}$, $W$ is partitioned into blocks $B_k$ with $\text{rows}(B_k) \le M$, $\text{cols}(B_k) \le N$.
• Resource and Partitioning Constraints:
  • Each computational tile/block must fit crossbar ($M$, $N$) (Sun et al., 2023, Bhattacharjee et al., 2018, Park et al., 12 Jan 2025).
• Objective Functions:
  • Area minimization: $\min \sum_j C_j y_j$ where $C_j$ is the area of crossbar $j$ and $y_j$ its usage indicator (Pohl et al., 3 Mar 2025).
  • Throughput or latency minimization: e.g., min/max per-core runtime, makespan, or pipeline delay (Sun et al., 2023, Park et al., 12 Jan 2025).
  • Energy or EDP minimization: compute and data-movement energy per completed inference (Park et al., 12 Jan 2025).
  • Interconnection cost minimization: minimize the number of inter-crossbar routes or spike transmissions in SNNs (Pohl et al., 3 Mar 2025).
• Pruning and Sparsity Constraints:
  • For DNN accelerators, impose L₀ ($\|\cdot\|_0$) or L₁ regularization:

  $$\min_\beta \|Y - X\beta\|_2^2 \text{ subject to } \|\beta\|_0 \le r$$

  with combinatorial mask $\beta$ indicating which crossbars or columns are kept (Liang et al., 2018, Ankit et al., 2017).

• Non-Ideality and Endurance Objectives:

  • In endurance-aware mapping, maximize the minimum lifetime over all mapped memristors:

  $\max_M \min_{t,i,j} \frac{E_{i,j}}{a_{i,j}}$

  where $E_{i,j}$ is the endurance and $a_{i,j}$ the access frequency (Titirsha et al., 2021).

3. Algorithmic Techniques and Frameworks

Algorithmic approaches to crossbar-constrained mapping include:

• Graph Partitioning and Tiling: Partition large matrices (weights or adjacency graphs) in ways that maximize on-core utilization while respecting fan-in/fan-out and crossbar size. For SNNs, the map from neuron adjacency matrices to crossbar groups is optimized for local axon sharing and minimal interconnection (Pohl et al., 3 Mar 2025). In PIM/AI accelerators, layers are split into tiles and mapped to crossbar pools, with replication where beneficial (Sun et al., 2023, Park et al., 12 Jan 2025).

• Genetic Algorithms/Metaheuristics: Used to optimize multi-objective trade-offs (throughput, latency, energy, replication), as in the PIMCOMP and COMPASS compilers (Sun et al., 2023, Park et al., 12 Jan 2025).

• Integer Linear Programming (ILP/MILP): Enables globally optimal area and routing solutions for SNNs with homogeneous or heterogeneous crossbar architectures (Pohl et al., 3 Mar 2025), or communication bus binding for SoCs (0710.4671).

• Clustered Pruning and Co-Design: To maintain high crossbar utilization, “structured” pruning or co-design optimization is performed to force sparsity patterns into dense clusters that fit $M\times N$ arrays with minimal wastage, leveraging both algorithmic clustering methods (e.g., spectral, SCIC) and gradient-based weight reweighting (Ankit et al., 2017).

• Device-Aware Mapping and Compensation: Device/array non-idealities (parasitics, variation, stuck-at faults) are mitigated by column reordering based on sensitivity analysis (Agrawal et al., 2019), non-negativity-constrained decompositions (ACM) (Kazemi et al., 2020), or algorithmic weight remapping (differential encoding for fault tolerance) (Yuan et al., 2021).

• Calibration, Dataflow, and Peripheral Codesign: Post-mapping calibration (e.g., ADC/DAC, polynomial regression in (Zhang et al., 2019)) and dataflow scheduling for memory access/concurrent operations are integrated to ensure run-time correctness and maximize throughput.

The table below summarizes representative frameworks:

Domain/Framework	Mapping Core Principle	Optimization Target
DNN Accelerators (Liang et al., 2018)	L₀-pruning + crossbar-structural	Min. # crossbars, accuracy
PIMCOMP (Sun et al., 2023)	Tile/replica GA assignment	Thpt/latency/comm. balance
Heterog. SNN (Pohl et al., 3 Mar 2025)	ILP axon-sharing + area/routing	Min. area/routes/spikes
TraNNsformer (Ankit et al., 2017)	Clustered pruning+clustering	Area/energy, utilization
ReCross (Lai et al., 12 Sep 2025)	Replicated, co-occurrence tile	Energy, latency
ReVAMP/CONTRA [(Bhattacharjee et al., 2018)/(Bhattacharjee et al., 2020)]	Logic/BF/LUT tiling	Min. delay/area
eSpine (Titirsha et al., 2021)	KL+PSO + endurance modeling	Lifetime

4. Hardware Non-Idealities and Fault Tolerance

Robust crossbar-constrained mapping requires explicit modeling and mitigation of non-idealities, including:

• Wire and Access Resistance: Line/parasitic resistances cause data-dependent voltage drops; mapping algorithms rearrange or calibrate weight/kernels such that sensitive computations are steered to locations with minimal degradation (Zhang et al., 2019, Agrawal et al., 2019).

• Device Variation and Faults: In analog/memristive arrays, stuck-at faults, conductance variation, and write-endurance must be accommodated. Methods include redundancy, fault-tolerant mapping (differential encoding), unstructured or structured pruning to avoid mapping onto unreliable cells, and dynamic remapping for graceful degradation (Yuan et al., 2021, Kazemi et al., 2020).

• ADC/DAC Precision and Peripheral Energy: Peripheral selection is codeveloped with mapping. Optimizations such as dynamic-switch ADC (low-energy, variable-resolution conversion) are employed to match workload access patterns and crossbar operations (Lai et al., 12 Sep 2025).

• Calibration and Runtime Adaptation: Compensation schemes include regression-based calibration (mapping analog outputs to logical values), bit-aware or noise-aware training after mapping, and online adaptive remapping (Zhang et al., 2019, Bhattacharjee et al., 2022).

5. Co-Design with Network and Model Architectures

Successful crossbar-constrained mapping is intimately linked to structured network design or adaptive pruning and training:

• Structured Pruning and Clustering: By aligning sparsity into block patterns that tile efficiently (high utilization), co-training or retraining steps are required. Losses include L1/L0 regularization, utilization/flexibility penalties, or explicit cluster density terms (Ankit et al., 2017, Liang et al., 2018).

• Feature-Map and Input-Channel Reordering: Sorting and grouping input channels by computed importance concentrates essential computation in robust/sensitive crossbar slots, minimizing mapping-induced loss (Liang et al., 2018).

• Replication and Tiling Strategies: For deep DNNs, multiple replicas of layer-tiles may be allocated to balance data movement, activation buffering, or to satisfy bandwidth and capacity bounds (Sun et al., 2023, Park et al., 12 Jan 2025).

• Compiler and System Support: End-to-end software stacks (e.g., MaD for neuromorphic mapping (Gopalakrishnan et al., 2019), PIMCOMP for DNNs (Sun et al., 2023), COMPASS for resource-constrained inference (Park et al., 12 Jan 2025)) integrate crossbar-specific partitioning, mapping, and scheduling with model-level operators.

6. Empirical Performance, Trade-offs, and Design Guidelines

The ultimate validation of crossbar-constrained mappings lies in hardware-aware metrics—area, energy-delay product (EDP), accuracy loss, latency, and lifetime. Key empirical findings include:

• Area/Energy Scaling: Structured pruning and clustering deliver 28–72% reduction in area and 49–67% energy savings at ≤3% accuracy cost across ImageNet/CIFAR DNNs (Liang et al., 2018, Ankit et al., 2017). ILP-based mapping on SNNs with heterogeneous crossbars yields up to 75% area savings versus homogeneous rounding (Pohl et al., 3 Mar 2025).

• Accuracy Degradation: Under strong non-idealities, mapping/backprop co-design and extra steps (crossbar-column rearrangement, weight-constrained training) enable sparse models to retain regime-level accuracy, even with 20× crossbar compression rates (Bhattacharjee et al., 2022).

• Throughput and Latency: PIMCOMP achieves 1.6× throughput and 2.4× latency improvement by global balance of core/crossbar utilization (Sun et al., 2023), while ReCross achieves ~4× and ~6× improvements in embedding reduction workload latency and energy, respectively (Lai et al., 12 Sep 2025).

• Fault Tolerance: Pruning combined with differential mapping increases tolerable stuck-at-fault rates by nearly an order of magnitude compared to classical mappings (Yuan et al., 2021).

• Design Guidelines:

  • For analog arrays, limit crossbar size to balance utilization with voltage drop/variation.
  • Prefer clustering and co-pruning to maximize block density and utilization.
  • Incorporate device/peripheral models at mapping/training time (e.g., quantization, endurance, parasitic-aware conversion).
  • Schedule mapping in two steps: (1) minimize area/EDP under architectural constraints; (2) postprocess for routing, spike minimization, or peripheral match (Pohl et al., 3 Mar 2025, Park et al., 12 Jan 2025).
  • For scaling, use hierarchical or metaheuristic mappers (GA/PSO) to navigate trade-offs at system scale.

7. Broader Impact and Extensions

Crossbar-constrained mapping is foundational for several system domains:

• DNN and SNN Acceleration: It underlies virtually all modern neuromorphic and PIM accelerator compiler frameworks and provides the backbone for mapping arbitrarily large networks onto practical chip arrays (Ankit et al., 2017, Park et al., 12 Jan 2025).
• Logic-in-Memory: Area-constrained mapping (e.g., for MAGIC/IMPLY ReRAM logic) enables large Boolean networks to fit into physically plausible crossbar footprints while maintaining parallelism and energy scalability (Bhattacharjee et al., 2018, Bhattacharjee et al., 2020).
• On-Chip Communication: In NoC/interconnect design, window-based traffic-aware MILP mapping of endpoints achieves near-minimal resource with predictable/performance isolation, tunable for real-time or soft-QoS workloads (0710.4671).
• Quantum Information: Crossbar control architectures in quantum-dot arrays rely on mapping language and shuttling algorithms that, under local hardware constraints, can realize complex topological codes with finite (albeit linear-in-distance) overhead and competitive logical error scaling (Helsen et al., 2017).
• Emerging Reliability and Variability: Methods continue to be extended to account for transient reliability, process/voltage/temperature (PVT) corners, and run-time adaptation (online calibration or re-mapping), making crossbar-constrained mapping a dynamic and active research area.

This field remains a rich intersection of device modeling, large-scale optimization, and neural (and non-neural) architecture cooperation. The progress in this domain—spanning optimization algorithms, co-design techniques, and empirical validation—continues to dictate the achievable system-level efficiency and reliability of crossbar-based computing in contemporary and next-generation architectures (Liang et al., 2018, Sun et al., 2023, Ankit et al., 2017, Pohl et al., 3 Mar 2025, Park et al., 12 Jan 2025).