Completely Neural Computer

• Completely Neural Computers are general-purpose neural systems that integrate program storage, data processing, memory, and I/O using high-dimensional latent states.
• They leverage neural dynamics and vector operations to achieve Turing-completeness and unified program-data representation across digital, neuromorphic, and biocomputing platforms.
• CNC implementations demonstrate robust modular computation and energy efficiency but face challenges such as stable long-horizon execution and scalable hardware standardization.

A Completely Neural Computer (CNC) is a machine or system in which all core computational functions—program storage, data processing, memory, and I/O—are realized exclusively via neural or neural-inspired substrates. The CNC paradigm generalizes classical von Neumann and Turing models to unified, fully neural architectures, achieving general-purpose programmability and stable, reusable execution through learned or emergent runtime states. CNCs span digital silicon, neuromorphic analog, biocomputing, and differentiable neural network implementations, each aiming for the integration of compute and memory in a single, holistically trained system (Zhuge et al., 7 Apr 2026).

1. Formal Definitions and Fundamental Properties

A Completely Neural Computer is defined as a mature, general-purpose realization of a "Neural Computer" (NC), where program text, machine state, and all memory are latent variables within a learned, differentiable (or biologically embodied) substrate (Zhuge et al., 7 Apr 2026). The CNC is required to satisfy:

• Turing-completeness: CNCs are capable of universal computation, exemplified by architectures such as the Developmental Network (DN) that learns the transition function of a universal Turing machine via neural mechanisms (Weng, 2018).
• Unified latent runtime state: All working memory, control, and I/O context are encoded in high-dimensional latent vectors or spiking activity patterns, updated via recurrent dynamics or synaptic/biochemical plasticity.
• Program-data unity: Both "^^^^1^^^^" and "data" are storable, composable, and callable in the same neural substrate, either as high-dimensional vectors, neuroprogram slots, or spike-based memory (Zhuge et al., 7 Apr 2026, Le et al., 2020).
• End-to-end differentiability or neural plasticity: The entire CNC is trained or adaptively modified using gradient-based learning, Hebbian/LTP updates, or analogous biological learning mechanisms.

The CNC paradigm is contrasted with conventional computers, agents, and world models as follows:

Object	Organized around	Source of truth	Primary role
Computer	Explicit ^^^^1^^^^	Program text, machine state	Execute code
Agent	Tasks	External software/tools	Mediate task requests
World Model	Environment dynamics	State-transition model	Predict future states
Neural Computer	Learned runtime state	Latent state $h_t$	Unify I/O, compute, memory

(Zhuge et al., 7 Apr 2026)

2. Core Architectures and Mathematical Primitives

CNC instantiations span multiple architectural types:

• High-dimensional vector CNCs: All symbols, data, and instructions are $H$-dimensional vectors, with $H\gg1$ (e.g., $H=10^4$). Mathematical operations include vector addition ("bundling"), coordinatewise/circular binding ("Hadamard" or "convolution"), permutation, and similarity computation via dot product or cosine (Kanerva, 30 Mar 2025). Programs and data are merely vectors in a unified space, with memory as an associative high-dimensional RAM.
• Hardware-friendly hyperdimensional CNCs: Use semi-holographic integer-modular chains of length $n=d\,y$ over group $(\mathbb Z/p)^y$, with superposition by concatenation and binding by modular pairwise sums. Implemented with data-path primitives (MUX/DEMUX, modular adders), and control logic mirrored on ASIC microarchitectures (CoPUs) (Serb et al., 2019).
• Biological/physical neuron CNCs: Compute via neuronal logic gates and sequential circuits using spiking neuron models (e.g., Izhikevich formulations), with state encoded in patterns of tonic or silent spiking. Fundamental logic (NAND, SR latch, D flip-flop) are built from excitatory/inhibitory networks and spike time buffers (Basso et al., 2024).
• Trainable neural program CNCs: Store and compose modular program fragments in external slot-based memory, with runtime controlled by a recurrent neural network that selects and combines ^^^^1^^^^ via soft attention or singular-value coding (Le et al., 2020).
• Learned runtime neural computers: Maintain all state, memory, and interface context inside a Transformer-updated latent vector $h_t \in \mathbb R^d$, trained from I/O traces, and able to roll out screen/terminal state under user or environment actions (Zhuge et al., 7 Apr 2026).

These share a requirement for large vector or activity spaces, program-data unity, and the ability to represent, update, and invoke ^^^^1^^^^ within neural memory.

3. Program Storage, Memory, and Runtime Organization

CNC designs require unification of program and data memory:

• High-dimensional RAM: Memory is organized as a set of physical or latent locations, each associated with a high-dimensional address vector. Both read and write operations locate near-neighbor vectors and superpose or retrieve content. Biological correspondences are made to cerebellar cortex (granule and Purkinje cell layers) (Kanerva, 30 Mar 2025).
• Slot-based neural program memory: Programs are stored as vectors or matrix bases (e.g., singular vectors) in a collection of matrices, with neural controllers reading by content and writing via gradient-driven selective erasure and addition (Le et al., 2020).
• Neural flip-flop/circuit networks: Classical program state is maintained via recurrent excitation/inhibition in neuronal networks (e.g., SR latches, D flip-flops), where each bit or register is a spiking memory cell (Basso et al., 2024).
• Unified latent state: In learned-state CNCs, all memory, buffer, and program context are compressed into the state vector $h_t$, which is updated at each input-step by a neural transition function and decoded for output or I/O rendering (Zhuge et al., 7 Apr 2026).

A plausible implication is that program modularity, reuse, and retention are mediated via memory slots or vector subspaces, supporting continual learning and resistance to catastrophic forgetting (Le et al., 2020).

4. Computation, Control, and Reasoning

CNCs execute computation via a combination of:

• Algebraic vector operations—addition (superposition), coordinatewise binding, and permutation—allowing the construction of compositional data and program structures (Kanerva, 30 Mar 2025, Serb et al., 2019).
• Symbolic reasoning via neural dynamics: Sequences, conditionals, and control flow are encoded as pointer chains, learned transitions, or dynamic gating via recurrent networks or winner-take-all competition (Weng, 2018, Le et al., 2020).
• Explicit neural logic circuits: Digital logic is synthesized from neuronal gates, spike patterns, and tailored inhibition/buffer paths (e.g., NAND cascade, SR latches, clocked D flip-flops) (Basso et al., 2024).
• Neural program composition: Programs are constructed at runtime by selecting, weighting, and assembling basis ^^^^1^^^^, either as linear combinations of memory vectors or as singular-value matrices that are instantiated as operator weights (Le et al., 2020).
• Learned latent update dynamics: In modern NC implementations, a Transformer-based transition function $F_\theta$ drives the update, possibly supplemented by action/attention injections, external buffer reads, or targeted loss functions (diffusion, contrastive, cross-entropy) (Zhuge et al., 7 Apr 2026).

In the Developmental Network framework, neural control is defined by mapping sensory/motor pairs to new internal states via Hebbian self-organization and online winner-take-all learning, incrementally synthesizing the computation graph of a universal Turing machine (Weng, 2018).

5. Performance, Hardware, and Implementation Modalities

CNC platforms exhibit diverse hardware realizations and resource profiles:

• ASIC CoPU-based CNCs: Semi-holographic vector processing primitives (superposition and binding) are implemented with only multiplexing, modular adders, and MUX/DEMUX logic, avoiding multipliers. A single CoPU achieves $<6\,\mathrm{pJ}$ per 64-bit operation and $H$0 latency, with hardware reuse from standard CPU ALUs and register files. Arrays of CoPUs, coupled with associative memories and ANN blocks, form the system core (Serb et al., 2019).
• Neuronal circuit biocomputers: Logic gates and memory are physically instantiated in neuron-on-a-chip constructs, with digital states corresponding to tonic spiking/silence windows (e.g., "1" as 7.5 Hz spiking for 500 ms). Logic gate propagation is slow ($H$1150 ms), area is $H$2m$H$3, but metabolic burden is stable and operation is carbon-neutral (Basso et al., 2024).
• Hyperdimensional computing hardware: Each vector dimension can be realized as an analog or digital circuit element (e.g., 1-bit XOR gate, memristor, comparator). Associative memory uses crossbar arrays with parallel in-memory computing, readout, and thresholding. Energy per vector store/recall can reach $H$4 nJ, with capacity scaling to billions of locations (Kanerva, 30 Mar 2025).
• Trainable neural CNCs: Full differentiability enables implementation on GPU-accelerated tensor fabrics, with memory as learned slot matrices, routines as network parameters, and control by RNNs or Transformers. Training costs are high (tens of thousands of GPU hours), with state-of-the-art handling only simple short-horizon tasks (Zhuge et al., 7 Apr 2026, Le et al., 2020).

A plausible implication is that, while "silicon" CNCs far exceed biological speeds, their main virtues are unification of memory and compute and cheap vector operations; neuronal and biophysical CNCs achieve energy efficiency and carbon neutrality at the cost of speed and scale (Serb et al., 2019, Basso et al., 2024).

6. Applications, Capabilities, and Empirical Evaluation

CNCs have demonstrated the following empirical properties:

• General-purpose and modular computation: Capable of learning and composing modular ^^^^1^^^^ with robust reuse and continual learning capacity. On image and RL tasks, CNCs (e.g., Neurocoder) form learned decision-trees in program space, supporting program selection per class and outperforming mixture-of-experts or fixed hypernetworks (Le et al., 2020).
• Self-contained Turing-universality: DNs trained by experience attain a fully neural, grounded version of the universal Turing machine, learning one transition at a time and remaining optimal under resource constraints (Weng, 2018).
• Unified I/O management: NCs trained on CLI and GUI traces learn to align pixel outputs to actions, achieving high fidelity in text rendering and cursor tracking (e.g., 98.7% cursor accuracy with explicit supervision) and preserving legibility of terminal content in video streams (Zhuge et al., 7 Apr 2026).
• Adaptation to non-stationarity and continual learning: Program slot architectures allow task isolation, mitigating catastrophic forgetting and enabling rapid adaptation to new program distributions (Le et al., 2020).
• Biocomputing digital primitives: Neuronal circuits reliably encode, store, and propagate binary data as spike trains, maintaining stable operation without energy collapse and supporting finite-state sequential logic (Basso et al., 2024).

A table summarizing empirical CNC properties:

Task/Domain	CNC Capability	Representative Result
Modular computation	Program slot selection/dynamic	>16% improved retention (Le et al., 2020)
Universal computation	Neural UTM via DN	Resource-optimal, error-free when sufficient capacity (Weng, 2018)
GUI/CLI runtime alignment	Pixel-text, pixel-cursor accuracy	0.99 SSIM, 98.7% cursor (Zhuge et al., 7 Apr 2026)
Biocomputing logic/memory	NAND, SR-latch, D flip-flop	Stable spiking, 7.5 bits/s (Basso et al., 2024)

7. Open Challenges and Future Directions

Despite progress, CNCs confront several unresolved issues:

• Stable long-horizon execution: Current architectures are challenged by drift and compounding errors in latent state over many steps. Proposed mitigations include hierarchical gating, modular structures, and replay loops (Zhuge et al., 7 Apr 2026).
• Native symbolic/algorithmic reasoning: Arithmetic, discrete control flow, and algorithmic execution remain brittle; improved machine-native primitives (discrete gates, neurosymbolic modules) and hybrid integration with classical logic are under investigation.
• Durable, traceable program update: Persistent routine installation, execution traceability, and secure update mechanisms are critical for practical software engineering and robust operation.
• Hardware maturity and standardization: Absence of standardized high-dimensional RAM or neuromorphic memory hinders scale-up; research on memristor, nanowire, and crossbar architectures is ongoing (Kanerva, 30 Mar 2025).
• Scaling and synchronization in biocomputing: Managing propagation delays, buffer insertion, and metabolic constraints are necessary to scale neurally implemented logic (Basso et al., 2024).
• Programming model: Formulating algorithm specification directly in vector or spike algebra, rather than conventional sequential code, remains a central challenge.

Future research is directed toward sparse neural representations, hardware–software co-design, expanded task-level benchmarking, physically embodied CNCs, and hybrid systems integrating deep learning with neural computing cores (Kanerva, 30 Mar 2025, Serb et al., 2019, Zhuge et al., 7 Apr 2026).

• "Neural Computers" (Zhuge et al., 7 Apr 2026)
• "A semi-holographic hyperdimensional representation system for hardware-friendly cognitive computing" (Serb et al., 2019)
• "Neurocoder: Learning General-Purpose Computation Using Stored Neural Programs" (Le et al., 2020)
• "A Model for Auto-Programming for General Purposes" (Weng, 2018)
• "Autonomous Learning with High-Dimensional Computing Architecture Similar to von Neumann's" (Kanerva, 30 Mar 2025)
• "Embodied Biocomputing Sequential Circuits with Data Processing and Storage for Neurons-on-a-chip" (Basso et al., 2024)