Boolean Circuit Minimization

Updated 20 November 2025

Boolean circuit minimization is the process of reducing gate count, circuit depth, or area-delay while ensuring functional equivalence.
It employs both exact methods (e.g., brute-force, dynamic programming, MINLP) and heuristic techniques (e.g., SAT-based rewrites, structural hashing) for optimization.
Recent research integrates machine learning and search-based strategies to enhance synthesis efficiency and address complexity challenges in VLSI and logic verification.

Boolean circuit minimization is the algorithmic and theoretical problem of finding, for a given Boolean circuit $C$ (over $n$ inputs and $m$ outputs), an equivalent circuit $C'$ that realizes the same function while optimizing a size metric such as the total gate count. This problem is central to logic synthesis, VLSI/CAD, verification, and even cryptographic hardness. The fundamental goal is, for all $x\in\{0,1\}^n$ , to achieve $C'(x)=C(x)$ while reducing resources such as the number of AND gates, circuit depth, or area-delay product.

1. Complexity Landscape of Boolean Circuit Minimization

The general Boolean circuit minimization problem is $\Sigma_2^P$ -complete, placing it in the second level of the polynomial hierarchy and making it broadly believed to be intractable for unrestricted circuits. The decision version asks: Given a circuit (or formula) $\phi$ and an integer $k$ , does there exist an equivalent circuit $\psi$ of size at most $k$ ? For unrestricted propositional formulas (and hence circuits), this Minimum Equivalent Expression problem (MEE) is $\Sigma_2^P$ -complete under Turing reductions, as shown by Buchfuhrer and Umans (2011). For special cases, such as circuits built only from AND, OR, or XOR, minimization can fall into P, but outside these "clones" in Post's lattice, minimization is coNP-hard or $\Sigma_2^P$ -hard (Hemaspaandra et al., 2011).

In the constraint/CNF framework, if the circuit realizes a conjunction of specific relations (from a so-called "Schaefer class" such as bijunctive, Horn, dual-Horn, affine), minimization is tractable; outside these subclasses, the problem is NP-complete or worse. For monotone depth-3 formulas ( $\Sigma_3$ or $\Pi_3$ ), the hardness of minimization connects directly to the existence of explicit circuit lower bounds, highlighting a boundary between feasible and infeasible classes (Raviv, 2013).

2. Algorithmic Techniques: Classical and Modern

Exact Methods

For small circuits or restricted classes, exact minimization is possible via brute-force truth-table enumeration, dynamic programming over restricted formula classes, and mixed-integer nonlinear programming (MINLP). For example, the approach of (Dimopoulos et al., 2021) formulates multi-output, multi-level two-input Boolean gate minimization as an MINLP, where circuit synthesis is encoded as an optimization over binary and real variables subject to functional and acyclicity constraints. This method guarantees optimality (up to timeouts due to solver limitations) but is only practical for circuits of modest size due to the combinatorial explosion in variable counts.

The Quine–McCluskey (QM) and its modified variants remain canonical for two-level (Sum-of-Products) circuits, explicitly generating all prime implicants and essential prime implicants via tabular, systematic combination steps (Huang, 2014, Jadhav et al., 2012). The modified QM method introduces elimination sums (E-sums) for aggressively reducing unnecessary comparisons, yielding significant speed-ups for $n\ge8$ .

BDD-based methods can extract disjoint sum-of-products covers from the one-paths of a reduced ordered binary decision diagram (ROBDD), enabling efficient SOP or DSOP minimization for large functions, provided the variable ordering is well chosen (Sensarma et al., 2012). However, minimization quality is critically sensitive to the BDD topology.

Heuristic and Local Rewriting

For practical circuits well beyond the reach of exact algorithms, contemporary tools emphasize fast, local improvements. Cirbo (Averkov et al., 19 Dec 2024) offers both:

Low-effort heuristics: such as removal of dangling gates, structural hashing (merging duplicate gates), and classical ABC-style rewriting. These are very efficient (linear-time), but with no guarantee of optimality.
High-effort SAT-based local minimization: Cirbo and related frameworks apply exact SAT-based synthesis to small subcircuits of bounded size ( $k_{\text{max}}$ ), replacing them if an equivalent, smaller implementation is found. This "windowing" or "cut-based" approach leverages the exponential cost only on a manageable fraction of the circuit, yielding consistent improvements. Subcircuits typically of size 6 to 8 are considered.

A distinct trend, exemplified by Simplifier (Averkov et al., 24 Mar 2025), is the reliance on precomputed databases of all possible small subcircuits up to a fixed size (e.g., all functions of 3 inputs and 3 outputs), so that local rewrites can be executed in linear time by lookup. By enumerating $O(n)$ canonical subcircuits (so-called "3-principal subcircuits"), Simplifier achieves further reductions—average 4% over ABC-resyn2 for AIGs and up to 30% on raw BENCH circuits—with minimal overhead.

Simulation-Guided and Resubstitution Paradigms

Simulation-guided Boolean resubstitution exploits fast simulation to aggressively prune the space of candidate rewrites before invoking expensive, exact (SAT or BDD-based) checks. A representative technique (Lee et al., 2020) works as follows:

Resubstitution: For each node $i$ (computing $f_i$ ), define a set of "divisors" $D_i$ (functions available elsewhere in the circuit).
Candidate generation: Enumerate replacement functions from $D_i$ (e.g., $d$ , $\neg d$ , $d_1 \vee d_2$ , $d_1 \wedge d_2$ for $d,d_1,d_2 \in D_i$ ).
Simulation pattern filtering: Use a small, expressive set of input patterns $P$ (e.g., 500–2000 patterns) to prune any $g$ for which $g$ disagrees with $f_i$ on any $p \in P$ .
SAT validation: Only candidates passing all pattern checks are sent to SAT for full equivalence verification.

In empirical studies, simulation filters out more than 95% of illegal candidates, and the framework achieves up to 74% size reduction compared to state-of-the-art, with one or two orders of magnitude fewer SAT calls (Lee et al., 2020).

3. Specialized Minimization: Symmetric and Constrained Circuits

For circuits comprised solely of AND chains (as arise in prefix adders and symmetric circuits), the minimization problem lies in NP and is APX-hard already for small arity $k\leq 3$ , in contrast to the general problem's $\Sigma_2^p$ -completeness (Armbruster, 6 Jan 2024). Exploiting overlap among tree-shaped subcircuits across multiple outputs (e.g., overlapping carry trees in adders), specialized greedy and matching-based approximation algorithms achieve optimality bounds of $4/3$ for $k=3$ , $1.9$ for $k=4$ , and $2k/3$ for general $k$ .

These results clarify a distinct tractable frontier: multi-output, associative-gate circuits are much easier to approximate than completely general circuits, informing efficient synthesis for arithmetic datapaths.

4. Learning and Search-Based Minimization

Modern Boolean circuit minimization for industrial scale circuits utilizes offline and online machine learning combined with search:

INVICTUS (Chowdhury et al., 2023): Poses minimization as a finite-horizon sequential decision process where "states" are circuits and "actions" are logic synthesis transformations (e.g., rewrite, refactor, resubstitute, balance from the ABC toolkit). A policy is trained offline via model-based RL, using MCTS data on a large corpus of designs, and then used to bias MCTS at inference (minimization) time. An out-of-distribution detector determines when to trust the learned policy or fall back to uninformed search. This approach yields up to 30% ADP (area-delay product) improvement and 6.3× runtime reduction compared to state-of-the-art logic synthesis flows.
ABC-RL (Chowdhury et al., 22 Jan 2024): Further introduces explicit nearest-neighbor retrieval in embedding space to fine-tune the balance between the learned policy and search; a sigmoid-mixed $\alpha$ parameter determined by GCN-based similarity determines how much to incorporate learning. On standard benchmarks, ABC-RL achieves 25% geometric-mean ADP reduction (wins 16/20 designs outright) and up to 9× iso-QoR speedup, outperforming baselines such as online RL, simulated annealing, and pure MCTS.

These frameworks empirically demonstrate that learned controllers can universally outperform hand-tuned synthesis recipes, but must dynamically adapt to novel design topologies via embedding-based OOD detection and retrieval.

5. Manual and Symbolic Methods

Traditional symbolic methods (Karnaugh maps, Quine–McCluskey, and ESOP-grouping) remain instructive for small-variable-count functions, motivating the design of visual or ESOP-based minimization for quantum circuits (e.g., Q-Map (Hajjdiab et al., 2023)). However, the exponential scaling with $n$ restricts their practical utility.

Heuristic rewriting, such as the hill-climbing, simulated annealing, and iterated versions described in (Ionita et al., 2023), are effective for monotone formulas (especially in attribute-based encryption, where circuit leaf-count directly impacts decryption speed). Iterated, annealed heuristics can reduce formula size up to 68%.

6. Tool Integrations and Empirical Performance

State-of-the-art tools for Boolean circuit minimization combine several of these ideas:

Tool	Approach	Empirical Effect
Cirbo (Averkov et al., 19 Dec 2024)	Structural and SAT-based local rewrite	12% mean, up to 83% best reduction
Simplifier (Averkov et al., 24 Mar 2025)	Database-accelerated local search	4% over ABC-resyn2 (AIG), 30% (BENCH)
INVICTUS (Chowdhury et al., 2023)	Offline RL + OOD-aware tree search	19–22% ADP reduction, 2–6× faster
ABC-RL (Chowdhury et al., 22 Jan 2024)	RL + nearest neighbor retrieval	25% ADP reduction, up to 9× faster

These frameworks achieve state-of-the-art performance on industrial and arithmetic benchmarks (e.g., IWLS and EPFL suites). Cirbo utilizes exact SAT-based local synthesis up to $k_{\max}=8$ , supports various bases (AIG, XAIG), and consistently improves upon existing records. Simplifier is particularly efficient due to linear-time coverage of principal 3-input subcircuits.

7. Limitations, Open Problems, and Research Frontiers

Scalability: All exact minimization strategies face an inherent $2^n$ or worse scaling barrier. SAT-based local synthesis and database-driven rewrites scale polynomially in size(C) but do not guarantee global optimality.
Complexity-theoretic status: The complexity of the MCSP (Minimum Circuit Size Problem) remains open; a polynomial-time solution would collapse key cryptographic assumptions and provide circuit lower bounds (Raviv, 2013).
Multi-objective synthesis: Most existing results optimize only gate count or ADP; trade-offs with depth, power, and reliability are not yet incorporated explicitly in major frameworks.
Highly-structured classes: For depth-3 or higher formula/circuit classes (beyond DNF or CNF), fine-grained complexity and approximability remain elusive (Hemaspaandra et al., 2011, Raviv, 2013).
Database scaling: Precomputed database approaches such as Simplifier are currently practical for windows of size up to 3; scaling to larger windows (e.g., 4-in/4-out) would require breakthroughs in canonicalization and synthesis techniques.

Ongoing research includes embedding-based retrieval for synthesis recipes, meta-learning over circuit families, and integrating deep symbolic representation learning for both circuits and formulas, aiming to further close the gap to the global minimum in practical settings.

Key References: (Lee et al., 2020, Hemaspaandra et al., 2011, Armbruster, 6 Jan 2024, Averkov et al., 19 Dec 2024, Averkov et al., 24 Mar 2025, Chowdhury et al., 22 Jan 2024, Chowdhury et al., 2023, Sensarma et al., 2012, Raviv, 2013, Dimopoulos et al., 2021, Jadhav et al., 2012, Ionita et al., 2023, Hajjdiab et al., 2023, Huang, 2014)