Belenos: Dual Systems in Biomechanics and Photonics

• Belenos is a dual-referenced term defining both a finite-element biomechanics profiling toolchain and a programmable photonic processor, each with distinct methodologies and applications.
• In biomechanics, Belenos is used to pinpoint microarchitectural bottlenecks in FEBio simulations, informing accelerator co-design with metrics like IPC and cache sensitivity.
• In photonics, Belenos implements an eight-mode single-photon register with nested parity-check filters, achieving precise calibration and leakage suppression in interferometric meshes.

Searching arXiv for papers on "Belenos" to ground the article and check for relevant disambiguation. Belenos is a name used in recent arXiv literature for two distinct research artifacts in different technical domains. In computer architecture and computational biomechanics, it denotes a methodology and toolchain for bottleneck evaluation in patient-specific finite-element simulations executed with FEBio, with the explicit goal of translating workload characterization into accelerator-design recommendations (Chitsaz et al., 19 Sep 2025). In programmable photonic quantum information processing, it denotes Quandela’s cloud photonic processor, used to realize an eight-mode single-photon register and nested Walsh parity-check filters implementing the classical $[8,7,2]$ single-parity-check code and the $[8,4,4]$ extended Hamming code (Tully et al., 16 Jun 2026). The term therefore functions as a disambiguation label across two otherwise unrelated literatures.

1. Disambiguation and domain scope

Current arXiv usage attaches the name “Belenos” to both a biomechanics-oriented performance-characterization framework and a photonic hardware platform. The shared name does not imply a shared technical stack; the two referents belong to different problem classes, evaluation methodologies, and performance criteria (Chitsaz et al., 19 Sep 2025, Tully et al., 16 Jun 2026).

Usage	Domain	Defining description
Belenos	Finite-element biomechanics	Methodology and toolchain for pinpointing microarchitectural and system-level bottlenecks in FEBio simulations and translating them into accelerator recommendations
Belenos	Cloud photonic processor	Programmable $24$-mode interferometric mesh used to implement an eight-mode single-photon register and nested Walsh parity-check filters

The biomechanics usage is centered on sparse FEM execution, pipeline behavior, cache sensitivity, and domain-specific accelerator co-design. The photonic usage is centered on first-quantized path/mode encoding, code-subspace filtering, syndrome routing, and calibration-limited leakage suppression. For technical writing, the ambiguity is material: “Belenos” without qualification can refer either to an analysis framework for FEBio workloads or to Quandela’s photonic processor.

2. Belenos in finite-element biomechanics

In biomechanics, Belenos is defined as a methodology and toolchain for pinpointing the key microarchitectural and system-level bottlenecks in patient-specific finite-element biomechanics simulations, using the FEBio solver and combining workload characterization with accelerator-oriented interpretation (Chitsaz et al., 19 Sep 2025). Its targeted simulations are FEBio’s “Stage 2” solver on realistic biomechanical models, including eleven standard FEBio test cases spanning musculoskeletal models, soft-tissue deformation, and contact problems with $O(10^5)$–$O(10^6)$ degrees of freedom, together with an ocular biomechanics eye-model case study featuring nonlinear material laws and iterative Newton–Raphson solves.

The core computation consists of assembling sparse stiffness matrices, performing factorization or Krylov-subspace solves, and assembling global vectors. These workloads are challenging because irregular sparsity produces poor data locality and low cache reuse, while high arithmetic intensity is mixed with unpredictable memory access patterns. The workload family also exhibits dynamic control flow due to the wide range of mesh sizes and nonlinear material updates. At the application level, the requirements combine high throughput for many elements with low latency for interactive surgical planning.

Belenos profiles these workloads on an Intel Core i9-14900K using Intel VTune’s “Microarchitecture Exploration” analysis and instruments FEBio inside gem5’s full-system X86 simulator for parametric sensitivity studies. Its conceptual role is therefore not merely descriptive profiling: it is an end-to-end workflow intended to close the loop between domain workload properties and microarchitectural design choices.

3. Microarchitectural characterization, performance model, and co-design rules

The central empirical result in the biomechanics Belenos study is that FEBio workloads are predominantly back-end bound rather than front-end limited (Chitsaz et al., 19 Sep 2025). Using top-down metrics,

$$\mathrm{FE}_{\mathrm{bound}}=\frac{C_{\mathrm{FE\_stall}}}{C_{\mathrm{total}}}, \qquad \mathrm{BE}_{\mathrm{bound}}=\frac{C_{\mathrm{BE\_bound}}}{C_{\mathrm{total}}},$$

the study reports that for small meshes of $O(10^5)$ dof, $\mathrm{FE}_{\mathrm{bound}} \approx 13.1\%$ and $\mathrm{BE}_{\mathrm{bound}} \approx 59.9\%$. For large meshes of $O(10^6)$ dof, front-end pressure rises only slightly, to approximately $[8,4,4]$0 in worst cases, whereas back-end bound cycles grow to $[8,4,4]$1. The stated implication is that instruction fetch and decode are not the primary bottlenecks; the solver is heavily back-end and memory bound, increasingly so as mesh size grows.

The gem5 sensitivity studies vary pipeline depth and width, L1/L2 cache sizes and associativities, branch predictor types, and load/store queue sizes. Performance is tracked through IPC, normalized execution time, and MPKI, with configuration sensitivity expressed as

$[8,4,4]$2

The reported degradations are specific. Reducing L1 size from $[8,4,4]$3 KB to $[8,4,4]$4 KB increased $[8,4,4]$5 by up to $[8,4,4]$6, cut IPC by approximately $[8,4,4]$7, and slowed runtime by $[8,4,4]$8. Switching from a tournament to a simple bimodal branch predictor degraded IPC by $[8,4,4]$9 and produced $24$0. Halving load-queue entries from $24$1 to $24$2 caused a $24$3 slowdown by increasing memory-related back-end stalls. Narrowing issue width from $24$4 to $24$5 ports reduced peak IPC from $24$6 to $24$7 and yielded a $24$8 runtime increase on large models.

Belenos also introduces a roofline-style performance model for sparse FEM:

$24$9

where $O(10^5)$0, $O(10^5)$1, $O(10^5)$2 is peak FMA throughput, and $O(10^5)$3 is sustained memory bandwidth. The back-end bound fraction is parameterized as

$O(10^5)$4

From these measurements the study derives four architecture-aware co-design recommendations. First, it prioritizes back-end memory bottlenecks through near-memory scratchpads or 3D-stacked DRAM and a hardware gather-scatter unit to coalesce irregular memory accesses, with savings of up to $O(10^5)$5 of back-end stalls. Second, because $O(10^5)$6, it recommends a narrower, in-order or very shallow out-of-order pipeline rather than a deep, wide OoO engine, while scaling SIMD/FMA lanes to match element-level arithmetic such as $O(10^5)$7 per cycle. Third, it proposes custom caches and prefetchers tuned for sparse patterns, including a small direct-mapped “element cache” and stride-aware prefetchers keyed on mesh connectivity rather than linear addresses. Fourth, it recommends lightweight branch prediction, specifically replacing complex predictors with a two-bit local predictor because branch mispredictions account for less than $O(10^5)$8 of total stalls, allowing area and energy to be reallocated to memory structures.

4. Photonic Belenos as an eight-mode single-photon code platform

In photonics, Belenos refers to Quandela’s cloud photonic processor, whose programmable $O(10^5)$9-mode interferometric mesh is used to realize an eight-mode register for single-photon spatial-mode experiments (Tully et al., 16 Jun 2026). Eight modes, labeled $O(10^6)$0–$O(10^6)$1 in Perceval, are selected and logically indexed by the vertices of the three-cube $O(10^6)$2, that is, the bit strings $O(10^6)$3. A Gray-code Hamiltonian cycle on $O(10^6)$4,

$O(10^6)$5

fixes the internal mode order used by the neutral-sector core.

The encoding is first-quantized path/mode encoding. A single photon is prepared in a normalized superposition

$O(10^6)$6

where $O(10^6)$7 denotes one photon in mode $O(10^6)$8. Errors are modeled as additive perturbations on a single $O(10^6)$9, namely support-weight-$$\mathrm{FE}_{\mathrm{bound}}=\frac{C_{\mathrm{FE\_stall}}}{C_{\mathrm{total}}}, \qquad \mathrm{BE}_{\mathrm{bound}}=\frac{C_{\mathrm{BE\_bound}}}{C_{\mathrm{total}}},$$0 faults in the eight-dimensional mode basis.

The logical structures realized on the processor are classical codes embedded into the spatial-mode register. The zero-sum “neutral” subspace is

$$\mathrm{FE}_{\mathrm{bound}}=\frac{C_{\mathrm{FE\_stall}}}{C_{\mathrm{total}}}, \qquad \mathrm{BE}_{\mathrm{bound}}=\frac{C_{\mathrm{BE\_bound}}}{C_{\mathrm{total}}},$$1

equivalently the $$\mathrm{FE}_{\mathrm{bound}}=\frac{C_{\mathrm{FE\_stall}}}{C_{\mathrm{total}}}, \qquad \mathrm{BE}_{\mathrm{bound}}=\frac{C_{\mathrm{BE\_bound}}}{C_{\mathrm{total}}},$$2 single-parity-check code, with orthogonal projector

$$\mathrm{FE}_{\mathrm{bound}}=\frac{C_{\mathrm{FE\_stall}}}{C_{\mathrm{total}}}, \qquad \mathrm{BE}_{\mathrm{bound}}=\frac{C_{\mathrm{BE\_bound}}}{C_{\mathrm{total}}},$$3

The extended Hamming subspace is defined through the Walsh parity-check matrix

$$\mathrm{FE}_{\mathrm{bound}}=\frac{C_{\mathrm{FE\_stall}}}{C_{\mathrm{total}}}, \qquad \mathrm{BE}_{\mathrm{bound}}=\frac{C_{\mathrm{BE\_bound}}}{C_{\mathrm{total}}},$$4

for which

$$\mathrm{FE}_{\mathrm{bound}}=\frac{C_{\mathrm{FE\_stall}}}{C_{\mathrm{total}}}, \qquad \mathrm{BE}_{\mathrm{bound}}=\frac{C_{\mathrm{BE\_bound}}}{C_{\mathrm{total}}},$$5

identifying the classical $$\mathrm{FE}_{\mathrm{bound}}=\frac{C_{\mathrm{FE\_stall}}}{C_{\mathrm{total}}}, \qquad \mathrm{BE}_{\mathrm{bound}}=\frac{C_{\mathrm{BE\_bound}}}{C_{\mathrm{total}}},$$6 first-order Reed–Muller, or extended Hamming, code.

The hardware realization is expressed through three unitary components. A BALANCE separator $$\mathrm{FE}_{\mathrm{bound}}=\frac{C_{\mathrm{FE\_stall}}}{C_{\mathrm{total}}}, \qquad \mathrm{BE}_{\mathrm{bound}}=\frac{C_{\mathrm{BE\_bound}}}{C_{\mathrm{total}}},$$7 maps the uniform mode $$\mathrm{FE}_{\mathrm{bound}}=\frac{C_{\mathrm{FE\_stall}}}{C_{\mathrm{total}}}, \qquad \mathrm{BE}_{\mathrm{bound}}=\frac{C_{\mathrm{BE\_bound}}}{C_{\mathrm{total}}},$$8 to physical output port $$\mathrm{FE}_{\mathrm{bound}}=\frac{C_{\mathrm{FE\_stall}}}{C_{\mathrm{total}}}, \qquad \mathrm{BE}_{\mathrm{bound}}=\frac{C_{\mathrm{BE\_bound}}}{C_{\mathrm{total}}},$$9 and maps the neutral subspace $O(10^5)$0 into ports $O(10^5)$1–$O(10^5)$2; postselection on a click in port $O(10^5)$3 realizes projection onto the orthogonal complement, the DC dump. The sector-preserving core is extracted from two compiled neutral-sector circuits $O(10^5)$4 and $O(10^5)$5 as

$O(10^5)$6

and is described as real-orthogonal with $O(10^5)$7, fixing $O(10^5)$8 with eigenvalue $O(10^5)$9 and therefore leaving $\mathrm{FE}_{\mathrm{bound}} \approx 13.1\%$0 invariant. The parity separator $\mathrm{FE}_{\mathrm{bound}} \approx 13.1\%$1 is the normalized $\mathrm{FE}_{\mathrm{bound}} \approx 13.1\%$2 Hadamard/Walsh matrix whose first four rows are given by $\mathrm{FE}_{\mathrm{bound}} \approx 13.1\%$3, with ports $\mathrm{FE}_{\mathrm{bound}} \approx 13.1\%$4–$\mathrm{FE}_{\mathrm{bound}} \approx 13.1\%$5 carrying syndrome projections and ports $\mathrm{FE}_{\mathrm{bound}} \approx 13.1\%$6–$\mathrm{FE}_{\mathrm{bound}} \approx 13.1\%$7 carrying the code subspace.

5. Calibration, experimental metrics, and diagnostic behavior

The photonic Belenos experiments characterize both calibration systematics and code-filter performance across more than $\mathrm{FE}_{\mathrm{bound}} \approx 13.1\%$8 detections (Tully et al., 16 Jun 2026). In the BALANCE separator test, each computational-basis input mode $\mathrm{FE}_{\mathrm{bound}} \approx 13.1\%$9 was sent through $\mathrm{BE}_{\mathrm{bound}} \approx 59.9\%$0 and the dump probability on port $\mathrm{BE}_{\mathrm{bound}} \approx 59.9\%$1 was measured. Although the ideal dump probability is $\mathrm{BE}_{\mathrm{bound}} \approx 59.9\%$2, the eight modes showed a fixed-pattern bias with mean $\mathrm{BE}_{\mathrm{bound}} \approx 59.9\%$3 and spread approximately $\mathrm{BE}_{\mathrm{bound}} \approx 59.9\%$4 on individual modes. This separator calibration bias reappears in BALANCE readouts.

For neutral inputs such as $\mathrm{BE}_{\mathrm{bound}} \approx 59.9\%$5, $\mathrm{BE}_{\mathrm{bound}} \approx 59.9\%$6, and a balanced $\mathrm{BE}_{\mathrm{bound}} \approx 59.9\%$7-mode state, dump probabilities ranged from $\mathrm{BE}_{\mathrm{bound}} \approx 59.9\%$8 to $\mathrm{BE}_{\mathrm{bound}} \approx 59.9\%$9, with mean $O(10^6)$0. A non-neutral control, $O(10^6)$1, yielded $O(10^6)$2, above the ideal $O(10^6)$3 baseline because of the fixed pattern. Relative to the ideal DC-capture baseline, the destructive-interference suppression is approximately $O(10^6)$4; relative to the measured non-neutral control, it is $O(10^6)$5.

The soft-error experiment injects a tunable DC admixture of amplitude ratio $O(10^6)$6 onto a neutral state. The ideal dump response is

$O(10^6)$7

while the hardware response is fit by

$O(10^6)$8

with $O(10^6)$9, $[8,4,4]$00, and per-point residuals of order $[8,4,4]$01, matching the separator-bias offsets. The response is monotonic and calibratable across $[8,4,4]$02.

Repeated applications of $[8,4,4]$03 preserve the neutral sector to within calibration-limited scatter. Across depths from $[8,4,4]$04 to $[8,4,4]$05, the neutral dump remains at the $[8,4,4]$06–$[8,4,4]$07 level, and for a representative neutral input after up to three applications it stays at or below $[8,4,4]$08, far below the non-neutral control near $[8,4,4]$09. The non-monotonic fluctuation across depths is attributed to separate compilations and calibrations rather than to systematic per-cycle leakage; the reported interpretation is that the approximately $[8,4,4]$10 scatter is primarily a compilation-and-calibration systematic.

Parity-separator experiments further quantify code-subspace filtering and syndrome resolution. Code-space leakage into ports $[8,4,4]$11–$[8,4,4]$12 averaged $[8,4,4]$13, versus $[8,4,4]$14 for a non-code control, giving a suppression of approximately $[8,4,4]$15, or $[8,4,4]$16 on-chip. For single-face-parity-violating inputs, dominant-port selectivities were $[8,4,4]$17, $[8,4,4]$18, and $[8,4,4]$19, with off-diagonal confusion never exceeding $[8,4,4]$20.

A separate Hong–Ou–Mandel degradation episode functions as a coherence diagnostic. During a maintenance window, two-photon HOM visibility dropped from $[8,4,4]$21 to $[8,4,4]$22 and was later restored. For a fixed neutral preparation, dump probabilities changed from $[8,4,4]$23 in the calibrated state to $[8,4,4]$24 in the degraded state and then to $[8,4,4]$25 after restoration. The stated conclusion is that sub-percent suppression relies on coherent single-photon interference rather than on a simple intensity artifact.

6. Limits, misconceptions, and future directions

In the biomechanics setting, a common misallocation of effort would be to prioritize front-end sophistication or complex branch prediction. The Belenos measurements indicate the opposite emphasis: instruction fetch and decode are not the primary bottlenecks, branch mispredictions account for less than $[8,4,4]$26 of total stalls, and performance is dominated by irregular memory accesses and back-end resource starvation (Chitsaz et al., 19 Sep 2025). The open research avenues identified there are dynamic adaptation of prefetch patterns to evolving mesh refinements, integration of low-precision arithmetic for preconditioning steps, exploration of in-memory or near-data computing fabrics for further back-end stall reduction, and energy/performance trade-off studies under real-time surgical planning constraints.

In the photonic setting, the principal misconception would be to read the reported filters as a demonstration of full quantum error correction. The experiment explicitly verifies leakage suppression and syndrome routing, not error correction or protection against photon loss, and all probabilities are conditional on postselected single-photon detections (Tully et al., 16 Jun 2026). Loss is removed by postselection, only intensity rather than complex amplitude is measured at syndrome ports, and no active feed-forward correction, closed-loop recovery, multi-block concatenation, or fault-tolerance threshold testing is reported. The next steps identified for that platform are complex-amplitude syndrome readout, for example through a homodyne reference, active feed-forward gates, and integration with loss-protecting bosonic or loss-tolerant codes.

Taken together, the two uses of “Belenos” mark distinct styles of systems research. One links domain profiling of sparse FEM workloads to hardware specialization through VTune and gem5. The other uses a programmable interferometric mesh to realize nested parity-check filters in an eight-mode single-photon register. Their commonality lies only in nomenclature; their technical significance lies in the precision with which each isolates its own bottlenecks—memory-system pressure in FEBio-based biomechanics, and calibration- and compilation-limited leakage in programmable photonics.