Addition-Only Paradigm

• Addition-Only Paradigm is a computational framework that uses only addition (and limited negation) to perform operations typically requiring multiplication, ensuring constant-time and parallel digit processing.
• It achieves efficient error repair in coding theory and drives energy-efficient hardware designs by substituting multiplication with localized, bounded digit transformations.
• The paradigm underpins advancements in algorithms for RAM models, matrix multiplication, and self-attention mechanisms, leading to robust, low-power, and high-throughput computational systems.

The addition-only paradigm encompasses hardware, algorithmic, and number-theoretic methodologies for performing computational and algebraic operations entirely without multiplication, leveraging addition (and sometimes binary or ternary negation) as the primitive operation. This approach has been applied across high-performance numeration systems, memory repair in coding theory, algorithmic computation models, accelerator hardware, and energy-efficient machine learning architectures. Central to its design is the elimination of long-range carry propagation, expensive multiply units, and power-hungry logic, often enabling constant-time or highly parallel execution with bounded local state.

1. Foundations in Non-Standard Numeration Systems

Addition-only computation in non-standard numeration systems is established by constructing positional number representations with signed-digit alphabets, in which addition (and subtraction) of two expansions can be realized without chain carry-propagation, but rather through constant-time, localized digit transformations. The main theoretical result is that if the base $\beta$ is an algebraic number with $|\beta| > 1$ and no conjugate $\beta_j$ of unit modulus, there exist relations—specifically, a strong or weak representation-of-zero polynomial—that make such parallel addition possible with a bounded alphabet.

A prototypical construction uses an alphabet $\mathcal{A}$ tailored according to the coefficients of the aforementioned polynomial. Two main parallel algorithms (SRZ and WRZ cases) carry out the digitwise addition, then perform bounded-window digit rewritings using precomputed zero representations. All steps involve only additions and bounded translations; there is no multiplication, and the algorithms run in $O(1)$ parallel time per digit. For the Golden Ratio base, this construction can be refined to a minimal symmetric alphabet $\{-1, 0, 1\}$, through a sequence of digit-elimination phases, yielding an irreducible, addition-only, constant-time adder (Frougny et al., 2011).

These techniques enable high-throughput, neighbor-independent digit processing and generalized to subtraction and, with more complex rewritings, to on-line multiplication and division in such positional systems.

2. Addition-Only Computation in Coding Theory

Addition-only repair in locally repairable codes is achieved by designing finite field codes such that any codeword symbol can be recovered from a small set of neighbors through a single sum operation. In these codes, for each repair set $R(i)$, recovery is given by $c_i = -\sum_{j\in R(i)} c_j$, so only additions (or bitwise XORs in characteristic 2) are required. Two families of such codes are constructed:

• The first family achieves minimum Hamming distance $d = t+1$ (falling short of the Singleton-like bound by one) but allows universal repair by addition for any symbol.
• The second is optimal (attaining $d = n-k-k/r+2$) under mild field-size and length divisibility constraints.

Both constructions enable repair of single failures with only additions, entirely eliminating finite field multiplication/division from the repair path. Compared to pyramid codes and Tamo–Barg codes, these addition-only codes offer lower computational complexity and hardware demands at the potential cost of slightly reduced distance or stricter parameter constraints (Kiah et al., 2015).

3. Addition-Only Algorithms on RAM Models

In algorithmic theory, an addition-only RAM is a random-access machine restricted to the addition operation (apart from data movement and control), yet via linear-time preprocessing (building lookup tables), it emulates constant-time execution of all other basic arithmetic and bitwise operations on polynomial-size integers. This is formalized by showing that, after $|\beta| > 1$0 preprocessing, operations such as subtraction, multiplication, division, exponentiation, logarithm, square root, $|\beta| > 1$1-th root, and bitwise logic—each on $|\beta| > 1$2-bit words—can be carried out in $|\beta| > 1$3 time by a constant sequence of table lookups and additions.

The approach leverages tabular expansion of small-block operations and recursive reduction for large numbers, simulating the effect of more complex arithmetic using only addition and data movement. This demonstrates that, at unit cost, the addition-only RAM model is as powerful as standard RAM for all schoolbook arithmetic, modulo preprocessing overhead and the requirement that register values remain $|\beta| > 1$4 (Grandjean et al., 2022).

4. Addition-Only Matrix Multiplication and Hardware

Addition-only matrix multiplication is a technique for multiplying matrices entirely without hardware multiplier circuits, instead using a structured sequence of shift, prefix-sum, and addition operations. Each scalar product $|\beta| > 1$5 is replaced with a combination of alignment (removing power-of-two factors), sorting, deduplication, difference computation, recursive addition, scatter via pointers, and bit-shifting.

Experimentally, the mean number $|\beta| > 1$6 of additions (and shifts/copies) required per replacement of a multiplication approaches unity for large matrices (e.g., $|\beta| > 1$7 for $|\beta| > 1$8 and $|\beta| > 1$9 bits per word). Architecturally, this enables the elimination of multipliers from chips designed for dense matrix computation (e.g., ML accelerators), allowing a much greater number of parallel adder units, reduced silicon area, reduced energy consumption, and potentially order-of-magnitude increases in throughput for relevant matrix sizes and data widths. Pathological cases may marginally increase addition count, but alignment and data reuse mean the method is effective in large-scale machine learning domains (Cussen et al., 2023).

Operation	Traditional (MAC)	Addition-Only Paradigm
Scalar Product	Multiply-Add	Add-Shift-PrefixSum
Hardware Area	High (multiplier)	Low (adder)
Energy	High	5–10× lower
Throughput	Limited by area	3–6× more units/chip

5. Addition-Only Self-Attention in Neural Networks

In the context of spiking neural networks and efficient deep learning architectures, the Accurate Addition-Only Spiking Self-Attention (A²OS²A) mechanism realizes transformer self-attention blocks via hybrid binary/ternary spiking and ReLU neurons, entirely without multiplication in the token-token interaction. The architectural flow is:

• $\beta_j$0 head: binary spiking activations ($\beta_j$1)
• $\beta_j$2 head: ReLU activations ($\beta_j$3)
• $\beta_j$4 head: ternary spiking ($\beta_j$5)

The attention computation replaces dot products $\beta_j$6 and $\beta_j$7 with (sub)set summation and (signed) addition, no multiply, no softmax, and no scaling factor. Each step is thus addition-only over the relevant values. Empirically, this model attains 78.66% Top-1 accuracy on ImageNet-1K (A²OS²A Spiking Transf.-10-512, 36M parameters, 4 timesteps), outperforming prior SNN-Transformers with a 5–10× lower energy cost per attention head.

Limitations in current practice include the lack of explicit normalization (no row-wise sum to 1), hardware requirements for bipolar spikes, and potential stability issues for unbounded $\beta_j$8 values. Nonetheless, the architecture demonstrates that state-of-the-art accuracy for SNN-transformers can be attained with pure addition/subtraction—no products, division, softmax normalization, or scaling (Guo et al., 28 Feb 2025).

Model	Params (M)	Top-1 Acc (%)	Energy/Head (rel)
Spikformer-8-512 (’22)	29.7	73.38	$\beta_j$9
Spikingformer-8-512 (’23)	29.7	74.79	$\mathcal{A}$0
A²OS²A Spiking Transf.-8-512	29.7	76.28	$\mathcal{A}$1
A²OS²A Spiking Transf.-10-512	36.0	78.66	$\mathcal{A}$2

6. Addition-Only Algorithmics in Numeration and Automata

Beyond positional systems, the addition-only paradigm extends to non-integer numeration frameworks such as Ostrowski representations. Here, addition is computed via a fixed sequence of local digit passes (three scans: normalization, carry-propagation, and correction), each involving bounded-window digit transformations defined by explicit rules. When the defining number $\mathcal{A}$3 is quadratic, addition in its Ostrowski numeration can be fully recognized by finite automata, and definability in first-order logic with $\mathcal{A}$4 function coincides with automata-recognizability.

This connection yields decidability of the theory $\mathcal{A}$5 and allows efficient implementation of addition using only basic local rewriting rules that, again, require no multiplication, division, or long-range carries (Hieronymi et al., 2014).

7. Implications and Future Perspectives

The addition-only paradigm provides a template for designing numeration systems, error-correcting codes, RAM models, and hardware acceleration platforms where multiplication and other high-complexity operations are structurally absent from the critical path. This leads to constant-time or highly parallel algorithms, hardware simplification, reduced energy and area, and in many cases mathematical optimality (e.g., minimal symmetric alphabets, optimal code distance).

A plausible implication is that, in domains where addition-only computation suffices or can be engineered (e.g., via digit rewritings, precomputed tables, or quantized kernel architecture), one can achieve hardware and algorithmic acceleration, lower energy profiles, and increased robustness. However, fundamental limitations arise when unrestricted arithmetic, general division/modulo, or arbitrary data types are required, or where combinatorial explosion would occur in the necessary tables or state spaces.

Future research directions are likely to explore further hardware co-design, extension to other algebraic operations under similar paradigms, and complexity-theoretic characterizations of the boundaries of addition-only computability across computational models.