a‑SiC/SiN Photonic Platform

• a‑SiC/SiN Photonic Platform is a heterogeneous PIC that integrates low‑loss SiN for routing with a‑SiC for compact, high‑tunability functions.
• It employs adiabatic vertical couplers to achieve interlayer losses of 0.32±0.10 dB and over 4,444× higher integration density compared to pure SiN.
• The platform delivers 27× improved thermo‑optic tuning efficiency per unit length with a CMOS‑compatible, low‑temperature a‑SiC deposition process.

Searching arXiv for the cited platform paper and closely related background papers. arXiv Search Query: (Li et al., 14 Jul 2025) The a‑SiC/SiN photonic platform is a monolithically integrated, multilayer photonic integrated circuit architecture that combines high‑aspect‑ratio silicon nitride (SiN) waveguides with an upper amorphous silicon carbide (a‑SiC) layer in order to co‑realize extremely low propagation loss, very high integration density, and efficient thermo‑optic reconfigurability within one CMOS‑compatible stack. In the reported implementation, the platform achieves an on‑chip interconnection loss of $0.32\pm0.10$ dB per a‑SiC/SiN transition, an integration density increment exceeding 4,444‑fold relative to high‑aspect‑ratio SiN, and $27\times$ higher thermo‑optic tuning efficiency per unit length than the SiN photonic platform, while also supporting side coupling on SiN and grating coupling on a‑SiC (Li et al., 14 Jul 2025).

1. Material complementarity and design rationale

The platform is motivated by a specific division of labor between two dielectric photonic materials whose strengths are complementary rather than redundant. High‑aspect‑ratio SiN waveguides, exemplified by $100$ nm thickness and several‑$\mu$m width, are used where ultra‑low propagation loss is decisive. In optimized high‑aspect‑ratio SiN, propagation loss is as low as $10^{-3}$–$10^{-1}$ dB/cm and intrinsic resonator $Q$ reaches $4.22\times10^8$. SiN also offers a wide transparency window from visible to telecom and CMOS compatibility, but its low refractive index, $n_{\text{SiN}} \sim 1.9$ at $1550$ nm, leads to weak confinement, large minimum bending radii, and constrained thermo‑optic tunability (Li et al., 14 Jul 2025).

Amorphous SiC provides the opposite set of trade‑offs. Its refractive index is tunable and typically $27\times$0 at $27\times$1 nm, with low linear absorption in telecom and visible, a large thermo‑optic coefficient, and strong third‑order nonlinearities. State‑of‑the‑art a‑SiC propagation loss is reported as $27\times$2 dB/cm at $27\times$3 nm, higher than ultra‑low‑loss SiN but compatible with compact functional sections. The same material family has also been reported at $27\times$4C ICPCVD with $27\times$5 at $27\times$6 nm, intrinsic ring $27\times$7, and optical losses between $27\times$8 and $27\times$9 dB/cm, establishing low‑temperature deposition as a practical route to hybrid photonic integration (Lopez-Rodriguez et al., 2023).

Material	Representative properties	Primary role in the platform
SiN	$100$0, $100$1–$100$2 dB/cm, $100$3 mm, $100$4C	Long routing, delay lines, ultra‑low‑loss passive functions
a‑SiC	$100$5, $100$6 dB/cm, $100$7 $100$8m experimentally, $100$9 in the platform	Compact routing, thermo‑optic tuning, nonlinear functions, grating couplers

A common misconception is that the platform attempts to replace SiN with a‑SiC throughout the circuit. The reported architecture does not do so. It uses SiN for long, low‑loss routing, delay lines, and passive functions, and uses a‑SiC for tightly bent routing, thermo‑optic phase shifters, compact reconfigurable blocks, nonlinear optics, and grating couplers (Li et al., 14 Jul 2025). In that sense, “heterogeneous integration” denotes monolithic functional partitioning across vertically stacked materials rather than a uniform replacement of one platform by another.

2. Vertical architecture and interlayer interconnection

The realized device stack is a vertically integrated PIC on a Si substrate with thermal SiO$\mu$0 undercladding. The lower photonic layer is high‑aspect‑ratio SiN, with thickness $\mu$1 nm and width $\mu$2 $\mu$3m in standard single‑mode sections. Above a SiO$\mu$4 spacer and cladding lies the a‑SiC layer, with thickness $\mu$5 nm and width $\mu$6 nm in standard single‑mode sections. The refractive index difference is substantial, $\mu$7 at $\mu$8 nm, while both layers are embedded in SiO$\mu$9 with $10^{-3}$0 (Li et al., 14 Jul 2025).

The modal properties of the two layers are correspondingly different. The SiN waveguide cross section $10^{-3}$1 nm $10^{-3}$2 $10^{-3}$3 $10^{-3}$4m supports a large mode area of $10^{-3}$5 $10^{-3}$6, weak vertical confinement, and very large minimum bending radii. The a‑SiC cross section $10^{-3}$7 nm $10^{-3}$8 $10^{-3}$9 nm supports a mode area of $10^{-1}$0 $10^{-1}$1, much tighter confinement, and experimentally extracted $10^{-1}$2 $10^{-1}$3m, with simulations indicating $10^{-1}$4 $10^{-1}$5m (Li et al., 14 Jul 2025).

Efficient transfer between the layers is enabled by an adiabatic vertical interconnection coupler. In this structure, both the SiN and a‑SiC waveguides are laterally tapered so that the mode evolves adiabatically from one layer to the other through a phase‑matched supermode region. The optimal simulated design uses standard widths of $10^{-1}$6 $10^{-1}$7m for a‑SiC and $10^{-1}$8 $10^{-1}$9m for SiN, with center tip widths $Q$0 nm and $Q$1 $Q$2m. Simulated interconnection loss per transition is $Q$3 dB at $Q$4 nm (Li et al., 14 Jul 2025).

The approximate phase‑matching condition at the coupler center is expressed as

$Q$5

Experimentally, the interconnection efficiency is extracted by comparing a reference a‑SiC path to a path containing two a‑SiC/SiN transitions, giving

$Q$6

Using multiple nominally identical structures, the measured interconnection loss is $Q$7 dB per transition. Fabrication tolerance was studied over $Q$8–$Q$9 nm and $4.22\times10^8$0–$4.22\times10^8$1 $4.22\times10^8$2m, with added loss at most $4.22\times10^8$3 dB; the a‑SiC tip width is reported as more critical (Li et al., 14 Jul 2025).

This multilayer organization also allows SiN and a‑SiC circuits to cross in footprint. A plausible implication is that routing complexity can be shifted from planar crossing management to vertical mode transfer and layer assignment.

3. Integration density and thermo‑optic reconfigurability

A defining claim of the platform is that it relaxes the conventional coupling between low loss and large footprint. In the reported work, integration density is quantified by

$4.22\times10^8$4

Because device footprint for ring resonators, spirals, and routing bends scales roughly as $4.22\times10^8$5, this metric captures the area penalty of large bending radii. Using $4.22\times10^8$6 mm for $4.22\times10^8$7 nm thick, $4.22\times10^8$8 $4.22\times10^8$9m wide high‑aspect‑ratio SiN and $n_{\text{SiN}} \sim 1.9$0 $n_{\text{SiN}} \sim 1.9$1m for $n_{\text{SiN}} \sim 1.9$2 nm $n_{\text{SiN}} \sim 1.9$3 $n_{\text{SiN}} \sim 1.9$4 nm a‑SiC, the density ratio is

$n_{\text{SiN}} \sim 1.9$5

which is the basis of the reported $n_{\text{SiN}} \sim 1.9$6-fold integration density increment (Li et al., 14 Jul 2025).

The same partitioning applies to thermo‑optic tuning. The induced phase shift is written as

$n_{\text{SiN}} \sim 1.9$7

with

$n_{\text{SiN}} \sim 1.9$8

On the same chip, the authors measured a‑SiC rings of radius $n_{\text{SiN}} \sim 1.9$9 $1550$0m and SiN rings of radius $1550$1 $1550$2m under a global temperature sweep from $1550$3 to $1550$4C. The resonance shift was $1550$5 pm/$1550$6C for the a‑SiC ring and $1550$7 pm/$1550$8C for the SiN ring. After normalization by path length, the corresponding values are $1550$9 pm/$27\times$00C/$27\times$01m for a‑SiC and $27\times$02 pm/$27\times$03C/$27\times$04m for SiN, yielding the reported $27\times$05 higher thermo‑optic tunability per unit length in a‑SiC (Li et al., 14 Jul 2025).

The extracted material thermo‑optic coefficients are $27\times$06 and $27\times$07. An earlier low‑temperature a‑SiC study reported $27\times$08 for ICPCVD a‑SiC deposited at $27\times$09C and $27\times$10 for PECVD a‑SiC at $27\times$11C, reinforcing the view of a‑SiC as a practical thermal tuning layer above SiN (Lopez-Rodriguez et al., 2023).

The platform comparison reported in Table I places the a‑SiC/SiN power per $27\times$12 phase shift at $27\times$13 mW, versus $27\times$14 mW for high‑aspect‑ratio SiN, $27\times$15 mW for moderate‑confinement SiN, and $27\times$16 mW for standard $27\times$17-nm Si (Li et al., 14 Jul 2025). This suggests that the heterogeneous platform aims to approach silicon‑like reconfigurability while retaining SiN‑class low‑loss routing.

4. Optical interfacing, propagation loss, and resonant performance

The platform exploits different fiber‑to‑chip coupling strategies on its two constituent layers. On SiN, the preferred approach is edge or side coupling through inverse tapers. The standard SiN waveguide mode area is $27\times$18 $27\times$19, while SMF‑28 has mode area $27\times$20 $27\times$21 at $27\times$22 nm. By tapering the SiN waveguide to a tip width $27\times$23 nm, simulated coupling efficiency per interface reaches up to $27\times$24 for zero fiber gap. Experimentally, two edge couplers connected by a $27\times$25 bend yield normalized transmission up to $27\times$26 with the taper, versus $27\times$27 without it, corresponding to an approximately $27\times$28 improvement in fiber‑to‑chip coupling efficiency (Li et al., 14 Jul 2025).

On a‑SiC, the preferred interface is a surface grating coupler. The demonstrated gratings are apodized, with period $27\times$29 $27\times$30m and line‑width apodization $27\times$31 ranging from $27\times$32 to $27\times$33 nm for one set of devices and from $27\times$34 to $27\times$35 nm for another. Fibers are placed at $27\times$36 to chip normal. Measured maximum normalized output is $27\times$37 at $27\times$38 nm across two gratings, and $27\times$39 around $27\times$40 nm. Fabry–Perot oscillations are observed and attributed to reflections between fiber and grating coupler, indicating that back‑reflection engineering remains relevant (Li et al., 14 Jul 2025).

Propagation loss in both layers is inferred from resonator measurements. The intrinsic quality factor is given by

$27\times$41

and the corresponding propagation loss is

$27\times$42

The heterogeneous platform inherits the contrast between current PECVD a‑SiC, with $27\times$43 dB/cm typical at $27\times$44 nm, and high‑aspect‑ratio SiN in the $27\times$45–$27\times$46 dB/cm regime (Li et al., 14 Jul 2025).

Related a‑SiC resonator work illustrates the compact, high‑finesse behavior available in the material system. In an ultrasound‑sensing implementation using $27\times$47 nm $27\times$48 $27\times$49 nm a‑SiC waveguides, $27\times$50 $27\times$51m radius rings reached FWHM $27\times$52 pm, loaded $27\times$53, FSR $27\times$54 nm, and finesse $27\times$55, with a linear array of $27\times$56 resonators coupled to a single bus waveguide (Erdogan et al., 6 Jul 2025). This suggests that compact a‑SiC resonant blocks are compatible with dense wavelength‑multiplexed architectures, even though the a‑SiC/SiN platform paper itself focuses on interconnection, coupling, and thermo‑optic characterization rather than sensor arrays.

5. Fabrication flow and CMOS compatibility

The fabrication sequence is organized so that all high‑temperature steps are completed before the a‑SiC layer is added. The reported flow is consistent with standard CMOS photonics practice: a Si wafer with thermal SiO$27\times$57 undercladding is used; the SiN layer of $27\times$58 nm is deposited by LPCVD or an equivalent high‑quality process; SiN waveguides are patterned and etched; a high‑temperature anneal of at least $27\times$59C reduces N–H and Si–H absorption; and SiO$27\times$60 cladding may be planarized by CMP if needed. The a‑SiC layer is then deposited at low thermal budget, $27\times$61–$27\times$62C, patterned, and aligned lithographically to the pre‑existing SiN structures (Li et al., 14 Jul 2025).

The importance of low‑temperature a‑SiC is independently established by low‑temperature ICPCVD deposition at $27\times$63C on $27\times$64 $27\times$65m thermal SiO$27\times$66, where the reported roughness is $27\times$67 nm, compared with $27\times$68 nm for PECVD films, and the process is described as allowing higher plasma densities at lower ion damage. That work explicitly demonstrates patterned a‑SiC deposition on top of SiN using a PMMA lift‑off process and reports a $27\times$69 $27\times$70m tapered a‑SiC/SiN waveguide mode converter with $27\times$71 simulated coupling efficiency at $27\times$72 nm (Lopez-Rodriguez et al., 2023).

Three fabrication issues recur throughout the literature. The first is stress and cracking in high‑aspect‑ratio SiN, addressed by optimized LPCVD conditions and crack‑stop structures. The second is surface roughness and scattering, addressed in SiN by CMP and careful etching, and in a‑SiC by smooth as‑deposited films and optimized plasma processes. The third is thermal budget sequencing: in the heterogeneous platform, all high‑temperature SiN processing occurs before low‑temperature a‑SiC deposition, which preserves compatibility with previously fabricated photonic layers and future back‑end metallization (Li et al., 14 Jul 2025).

A common misconception is that “heterogeneous integration” here implies transfer bonding. The process logic reported for a‑SiC/SiN is instead monolithic and deposition‑driven: SiN is fabricated first, then a‑SiC is deposited on top by a CMOS‑compatible CVD route (Li et al., 14 Jul 2025).

6. Functional scope and research significance

The platform is explicitly positioned for programmable photonics, quantum photonics, nonlinear optics, and related heterogeneous PIC applications. In programmable photonics and analog computing, the intended pattern is to implement dense meshes of Mach–Zehnder interferometers, phase shifters, tunable couplers, and switching networks in a‑SiC, while reserving SiN for low‑loss backplanes and long delay lines. The reduction in bend radius and the $27\times$73 higher thermo‑optic tunability per unit length directly address the footprint and power bottlenecks of pure high‑aspect‑ratio SiN reconfigurable meshes (Li et al., 14 Jul 2025).

In quantum photonics, the role division is similarly explicit. SiN is already established for ultra‑low‑loss quantum circuits, while the a‑SiC layer is proposed for compact phase shifters, switches, and nonlinear sources based on four‑wave mixing. The platform discussion also includes integration of nanowire quantum dots by pick‑and‑place, using a‑SiC circuits for routing and SiN for long optical paths (Li et al., 14 Jul 2025). A broader review of SiC photonics places this within a wider context in which SiC offers wide bandgap, high refractive index, strong $27\times$74 and $27\times$75, and compatibility with optically addressable defect centers, whereas SiN contributes lower loss and mature passive infrastructure (Yi et al., 2022).

For nonlinear optics, the platform rationale is based on the combination of a‑SiC’s large third‑order nonlinearity and small effective mode area with SiN’s ultra‑low‑loss transport. The nonlinear parameter is written as

$27\times$76

and the a‑SiC layer is specifically associated with strong Kerr nonlinearity, efficient four‑wave mixing, and potential on‑chip photon‑pair generation. The SiN layer, by contrast, is associated with low‑loss transport and complementary dispersion engineering (Li et al., 14 Jul 2025).

The broader significance of the platform lies in its role as a CMOS‑compatible heterogeneous photonic substrate rather than a single‑function device family. Earlier low‑temperature a‑SiC work proposed the same material as a hybrid overlay for ultralow‑loss thin SiN and LiNbO$27\times$77, with the explicit aim of using SiN for routing and delay and a‑SiC for local high‑confinement, tunable, and nonlinear functions (Lopez-Rodriguez et al., 2023). The monolithic a‑SiC/SiN platform realizes that division of functions experimentally at the PIC level.

Taken together, the reported metrics define the a‑SiC/SiN photonic platform as a vertically integrated architecture in which SiN supplies the ultra‑low‑loss transport layer and a‑SiC supplies compactness, tunability, and nonlinear strength, with low‑loss vertical transitions connecting the two. The resulting system is not a compromise layer stack; it is a deliberately stratified platform in which each material is assigned the optical functions for which it is most effective (Li et al., 14 Jul 2025).