Exchange-only qubit stabilized by a single-spin qubit

Abstract: Hybrid approaches that combine different spin qubit encodings offer promising advantages. In particular, the additional degrees of freedom available in exchange-only qubits and their extensions enable enhanced spin lifetimes and facilitate error detection through the use of auxiliary spins. We show that integrating Loss-DiVincenzo with exchange-only qubits provides a practical route to realizing these benefits while remaining compatible with spin-shuttling architectures. We further demonstrate how the singlet-only exchange-only qubit can be employed for error detection, and we present a fault-tolerant $π$-rotation about each of the three control axes of the (singlet-only) exchange-only qubit. By enabling error detection at the lowest encoding level, our approach effectively converts charge and nuclear noise into erasures, thereby suppressing error propagation and potentially enhancing the performance of quantum error-correction schemes. More broadly, our work establishes a new perspective on the singlet-only exchange-only qubit as a logical encoding, opening the door to fault-tolerant gate constructions and spin-tailored quantum error-correction protocols for semiconductor-based quantum computing.

• The paper develops hybrid exchange-only and Loss–DiVincenzo architectures that transfer gauge information, detect errors, and protect logical operations using auxiliary single-spin qubits.
• Flagged stabilizer readout of the singlet-only exchange-only qubit achieves a 3.5% pseudo-threshold under weight-one noise and reduces errors by up to an order of magnitude under weight-four noise below 0.9%.
• Simulations show repeated error-detection cycles can reduce memory errors by up to two orders of magnitude under quasistatic noise and enable fault-tolerant π rotations, while calibration demands and undetected multi-spin faults remain challenges.

Overview

This paper investigates hybrid spin-qubit architectures that combine Loss–DiVincenzo (LD) single-spin qubits with exchange-only (EO) and singlet-only exchange-only (SOEO) qubits, with the goal of enabling quantum error detection at the lowest encoding level. The authors demonstrate three main results: a protocol for transferring gauge information between an EO qubit and an LD qubit using simultaneous exchange pulses; fault-tolerant stabilizer readout of the SOEO qubit's $XXXX$ and $ZZZZ$ stabilizers using auxiliary LD spins, including flag-qubit protection; and fault-tolerant $\pi$-rotations about all three control axes of the SOEO qubit via a flagged SWAP construction. The central claim is that error detection at this level converts charge and nuclear noise into erasures, suppressing error propagation into higher-level codes such as the surface code.

Gauge transfer between LD and EO qubits

The EO qubit encodes two qubits: a primary logical qubit and a gauge degree of freedom corresponding to the total spin projection $S_z = \pm 1/2$. The paper shows that pulsing all three exchange couplings between the three EO spins and a fourth LD spin simultaneously to the same value $J$, for gate time $t_g = \pi/J$, implements an iSWAP between the LD spin state and the gauge information. Monte Carlo simulation ($10^4$ runs) of quasi-static exchange noise quantifies the infidelity as a function of $\sigma/J$.

A key application is a repeated projection protocol: initialize the LD spin in $\ket{\downarrow}$, apply the iSWAP, measure it. Measuring $\ket{\downarrow}$ leaves the EO qubit untouched if it resides in the $ZZZZ$0 subspace; measuring $ZZZZ$1 projects the qubit onto that subspace. Simulations show that repeating this cycle extends the EO qubit lifetime relative to idling, provided the relative gate noise is sufficiently low — behavior consistent with the quantum Zeno effect. The authors note a practical caveat: realizing the required star-shaped coupling demands high-precision calibration in a real device, which they identify as a significant implementation challenge.

Fault-tolerant stabilizer readout of the SOEO qubit

The SOEO qubit encodes one logical qubit in the total-spin-$ZZZZ$2 subspace of four spins. Its stabilizers, $ZZZZ$3 and $ZZZZ$4, coincide with those of the $ZZZZ$5 code, though only one logical qubit is used while the remaining degree of freedom acts as a gauge. Because these stabilizers commute, they can be measured concurrently — unlike the non-commuting $ZZZZ$6 and $ZZZZ$7 of the three-spin EO qubit.

Since SOEO operations rely exclusively on exchange pulses, single-spin rotations are unavailable natively; the readout circuits therefore use two auxiliary LD spins — one syndrome ancilla and one flag qubit for fault tolerance — shuttled between the SOEO qubit and LD control zones. CNOT gates between spins are constructed from $ZZZZ$8 ($ZZZZ$9) pulses plus single-spin gates on the LD ancilla, exploiting the fact that applying $\pi$0 to all four data spins is itself a stabilizer operation requiring no physical execution.

Under circuit-level depolarizing noise with incoming weight-one faults, the flagged readout exhibits quadratic scaling of the postselected error probability, confirming fault tolerance, with a pseudo-threshold of $\pi$1. For incoming weight-four depolarizing faults — a worst case motivated by native multi-spin exchange pulses — quadratic scaling is not recovered because some dangerous errors remain undetected (63 of 243 possible multi-weight faults), but flagged QED still reduces the qubit error rate by up to one order of magnitude below $\pi$2. Notably, unflagged QED performs worse than no measurement at all under weight-four noise, underscoring the necessity of flag protection.

Memory experiment

A memory simulation over repeated QED cycles incorporates idling errors derived from a semiclassical model of nuclear magnetic noise via a Magnus/cumulant expansion. Two effective depolarizing models result: type-(i), $\pi$3, from quasistatic or $\pi$4 spectra; and type-(ii), linear-in-time decay, from white spectra. The characteristic times are chosen representative of silicon experiments rather than any specific device.

For type-(i) noise, the QED protocol yields both higher acceptance rates than pure idling and a qubit error reduction of up to two orders of magnitude, attributed to the Zeno effect: the cycle time $\pi$5 lies below the Zeno time $\pi$6. For type-(ii) noise, no Zeno effect arises (as expected, since survival decays linearly at short times); acceptance rates drop relative to idling, but accepted runs still exhibit nearly an order-of-magnitude lower error. Thus the protocol trades retention rate for fidelity in the white-noise case, while improving both in the quasistatic case.

Fault-tolerant $\pi$7-rotations

Because SOEO native gates act on multiple spins within a code block, transversal single-qubit gates do not exist natively, and no fault-tolerant gate set had been established. The paper observes that a SWAP between two spins is Clifford and can be made fault tolerant via a triangular arrangement with an arbitrary-state auxiliary spin, ensuring the two data spins never share a SWAP operation. A $\pi$8-pulse on exchanges $\pi$9, $S_z = \pm 1/2$0, or $S_z = \pm 1/2$1 realizes logical $S_z = \pm 1/2$2, $S_z = \pm 1/2$3, and $S_z = \pm 1/2$4, respectively.

Simulations of the fault-tolerant $S_z = \pm 1/2$5 gate against a direct SWAP show comparable acceptance but quadratic scaling versus linear, with error suppression up to two orders of magnitude for $S_z = \pm 1/2$6–$S_z = \pm 1/2$7. A notable structural finding: whereas $S_z = \pm 1/2$8 is Clifford, $S_z = \pm 1/2$9 and $J$0 lie outside every finite level of the Clifford hierarchy, yet are implemented fault tolerantly here — a capability absent from standard codes such as the Steane or surface codes without magic states or code switching. Whether this can feed into magic-state injection or code-switching protocols remains open.

Limitations and open questions

The paper concedes several constraints. The gauge-transfer gate requires simultaneous, equal-strength star-shaped exchange couplings whose calibration precision may be prohibitive. The stabilizer readout does not detect all errors under realistic multi-spin noise: roughly 25% of possible multi-weight faults remain undetected, precluding quadratic suppression under weight-four incoming noise. Standard SOEO readout via singlet-triplet measurement on spin pairs is not fault tolerant, and a fully fault-tolerant decoding strategy for this final measurement is deferred to future decoder design. The identified fault-tolerant gate set — three $J$1-rotations plus SWAP — falls far short of universality; whether a fault-tolerant CNOT between EO/SOEO qubits or additional fault-tolerant single-qubit gates exist remains unresolved. Finally, the idling noise model reproduces short-time decay characteristics but discards temporal correlations of quasistatic processes, and gate errors are modeled as time-independent averages rather than the time-dependent rates implied by quasistatic accumulation.

Conclusion

This work establishes the SOEO qubit as a logical encoding amenable to low-level, fault-tolerant error detection within shuttling-compatible hybrid architectures. The flagged stabilizer readout achieves a 3.5% pseudo-threshold under weight-one noise, converts dominant charge and nuclear noise into erasures beneficial for surface-code concatenation, and provides fault-tolerant non-Clifford rotations unavailable in conventional stabilizer codes. The remaining gaps — incomplete error coverage under multi-spin noise, calibration demands of the gauge-transfer gate, and the absence of a fault-tolerant entangling gate — define the concrete open problems for extending this approach toward universal fault-tolerant semiconductor quantum computing.