AtomFlow: An End-to-End FPGA-Based Control Architecture for Neutral Atom Quantum Computers

Abstract: Neutral Atom Quantum Computing (NAQC) is an emerging modality for scalable quantum computation, valued for its long coherence times and the naturally identical atomic qubits. However, one of the main drawbacks is its slow execution rate, dominated by lengthy classical processing tasks, such as fluorescence imaging, cooling, and atom rearrangement. We address this bottleneck with AtomFlow, a field-programmable gate array (FPGA)-based control architecture that consolidates fluorescence-image analysis and a newly developed atom-rearrangement algorithm onto a single Zynq UltraScale+ device. By co-locating the two stages on the same board and emitting rearrangement moves in a streaming fashion as soon as they are computed, AtomFlow eliminates the round-trip latency of conventional host-mediated pipelines. Evaluated on a 16x16 atom array, AtomFlow achieves an end-to-end latency of 25.3 ms with a first-move latency of 4 ms and an average move generation of 1 ms. Furthermore, our scalability analysis demonstrates that the architecture can readily support larger atom arrays within a single-board resource budget.

• The paper presents AtomFlow, an end-to-end architecture on one Zynq UltraScale+ RFSoC that combines fluorescence-image analysis with streamed atom rearrangement and removes host round trips from the rearrangement pipeline.
• The system processes a 16×16 array in 25.3 ± 0.2 ms, generates its first move in 4 ms, and averages 1.01 ms per move while using 29.6% of LUTs, 21.1% of flip-flops, 20.8% of BRAMs, and 11.1% of DSPs.
• The results show that streaming can hide generation time behind slower physical moves, but faster AOD execution, full camera-to-AWG hardware closure, and validation under repeated QEC workloads remain open challenges.

AtomFlow is an FPGA-based control architecture that unifies fluorescence-image analysis and atom rearrangement for neutral atom quantum computers (NAQCs) on a single Zynq UltraScale+ RFSoC, eliminating host-mediated round-trip communication from the initialization pipeline. The work addresses a well-identified bottleneck: while prior efforts accelerated atom detection and rearrangement separately, no integrated end-to-end FPGA solution existed. On a 16×16 atom array requiring 22 moves, AtomFlow achieves a 25.3 ms end-to-end latency with a 4 ms first-move latency and an average move-generation rate of 1.01 ms per move.

Motivation and problem statement

In NAQC control pipelines, initialization and readout dominate system latency. Atoms are loaded stochastically into optical tweezers at roughly 50% occupancy, so each experimental cycle requires fluorescence imaging to detect defects, followed by parallel rearrangement into a defect-free target geometry using acousto-optic deflector (AOD) tweezers. Under quantum error correction (QEC), repeated mid-circuit measurement–feedback loops make these latencies critical. The authors observe that conventional host-centric implementations force every control loop—initialization, circuit execution, and feedback—to cross the software/FPGA boundary, and they argue that software-only optimizations are therefore insufficient. Prior FPGA accelerators for image processing and rearrangement optimized the two stages in isolation; AtomFlow's contribution is their integration on one device, with a streaming interface that emits rearrangement moves as soon as they are computed so that move generation overlaps physical move execution.

Background: imaging and rearrangement

Fluorescence imaging serves both initial atom detection and state-dependent readout, where atoms in $|1\rangle$ scatter photons while those in $|0\rangle$ remain dark. Because exposure time must be minimized to limit heating, photon counts are low and detection is noisy, imposing a fidelity–exposure trade-off. Physical move execution takes 120–800 μs of constant trap-transfer time plus distance-dependent transport at speeds between 54 μm/ms and 550 μm/ms, often exceeding 1 ms per composite move. This execution budget motivates interleaving: if the next move can be generated faster than the current one executes, generation overhead vanishes except for the first move.

The rearrangement algorithm is adapted from the authors' HiPARS library, specifically row-by-row lattice sorting. A sorting channel wide enough for free atom movement sweeps the array; unusable atoms are ejected, useful atoms are shifted toward user-specified target sites, and surplus atoms are parked outside the computation zone for later deficiency resolution. Moves come in two-, three-, and four-step variants corresponding to channel clearing, removal, and cross-channel transport, respectively.

Architecture

AtomFlow comprises three modules orchestrated by the ARM processing system (PS) over AXI4-Lite: the previously published FPGA-based Image Processing Module performing PSF-deconvolution-based per-site emission reconstruction, a new Atom Rearrangement Engine implemented in HLS, and a Control Interface Module handling binarization against a calibrated threshold and mode switching between initialization and readout without extra cost.

The rearrangement engine operates on binary arrays up to 256×256 sites via a four-state FSM clocked at 100 MHz sharing a time-multiplexed datapath. Key design choices include:

• Classification (S0): a per-site sweep builds targetSites, usableAtoms, and unusableAtoms lists in dual-port BRAM, using a 5×5 neighborhood mask evaluated at 25 sites per cycle with cyclic array partitioning.
• Corridor clearing (S1): occupied corridor sites are ejected as two-step parallel moves, applied immediately to the live state buffer.
• Channel sorting (S2): discard, scatter/park, and fill operations resolve against the S0 lists in place, with the move encoder unrolled by a factor of two and dual-port BRAM enabling same-cycle read/write compaction.
• Deficiency resolution (S3): donor–recipient transfers via four-step double-elbow moves, skipped entirely when all targets are filled after S2.

All inner loops sustain initiation interval II=1, and vertical/horizontal traversals are emitted as separate hardware instances feeding shared comparators, removing axis-selection multiplexers from the critical path. Each ParallelMove is packed into a 320-byte AXI-Stream packet of up to four steps carrying up to 16 column and 16 row selections as 16-bit signed integers, with tlast asserted every fifth beat. Moves stream out in execution order without DDR write-back, allowing the AWG to act on early moves while later ones are still being computed.

An important caveat: in the current implementation the PS mediates data movement and result verification; the fully hardware-closed loop—with camera input, direct AWG drive, and on-FPGA feedback analysis—is presented only as planned extensions (dashed paths in the architecture diagram). The evaluation therefore measures a software-in-the-loop configuration.

Evaluation

Verification proceeds through a simulated-image workflow: ground-truth occupancy generates a synthetic image, detection reconstructs positions, the rearrangement module computes moves, and applying those moves to the ground-truth array reproduces the target geometry exactly. Correctness holds provided sufficient atoms and, in some cases, parking spots exist—a dependency the paper states plainly rather than treating as universal.

Latency was measured on a ZCU216 across 10 runs of a 16×16 test case:

Stage	Latency (ms)	Share
Image analysis	2.4 ± 0.0	9.5%
Control interface	0.6	2.4%
Rearrangement	22.3 ± 0.2	88.1%
Total	25.3 ± 0.2	100%
First-move latency	4	—

Rearrangement dominates at 1.01 ms per move. Using two execution-time models (fast: 120 μs transfer plus 0.55 μm/μs transport; slow: 800 μs plus 0.054 μm/μs), the timeline analysis shows that under the slow model the engine always produces moves ahead of demand, with excess moves queuing—so only first-move latency matters. Under the fast model, however, gaps appear where the AWG waits for the next move; the authors concede that further optimization is needed before generation time is fully hidden behind physical execution for fast backends. This is the paper's most significant open performance question, since improved AOD–SLM transfer times would erode the current margin.

Resources: post-place-and-route utilization totals 29.6% LUTs, 21.1% FFs, 20.8% BRAMs, and 11.1% DSPs. Image analysis dominates DSP usage (447 of 475) due to PSF-reconstruction multiplications and consumes the most LUTs/FFs (87.6k/124.2k), while rearrangement dominates BRAM (202 tiles per the hierarchical report) for state arrays and move buffers. Note a minor internal inconsistency: the resource table lists total BRAM as 46 tiles (4.3%), which conflicts with the text's claim of 202 tiles and 20.8%; readers should treat the BRAM accounting cautiously.

Scalability: sweeping array dimension $N$ from 16 to 256 shows only BRAM growing approximately linearly (the $N^2$ buffer demand flattened by block quantization), while LUT/FF/DSP remain nearly flat because datapath width is bounded by fixed AOD channel counts. These figures are pre-optimization HLS estimates—an explicit upper bound—and the authors note the image-analysis caching strategy could offset BRAM pressure at larger sizes. They also acknowledge that image analysis, not rearrangement, becomes the scaling bottleneck beyond current limits, though they expect no fundamental obstacle.

Limitations and open questions

Several limitations bear directly on the results. First, the measured latencies reflect a software-in-the-loop deployment; the claimed elimination of host round-trips applies to the rearrangement stage only, since the PS still fetches data and verifies output, and the camera/AWG/control-processor integration remains future work. Second, correctness relies on adequate atom supply and parking capacity, conditions not guaranteed under heavy loss. Third, the interleaving benefit is model-dependent: it holds fully only for conservative (slow) backend parameters, and the fast-model case exposes residual generation bottlenecks. Fourth, scalability numbers are HLS estimates rather than post-implementation measurements, and the unified scalability study covering both stages is precluded by differing experimental requirements. Finally, whether the streaming interface sustains its latency advantages when connected to real AWG hardware, and how the design performs under QEC-grade repeated readout cycles, remain unmeasured.

Conclusion

AtomFlow demonstrates that fluorescence-image analysis and parallel atom rearrangement can be consolidated onto a single FPGA with streaming move delivery, achieving millisecond-scale move generation (1.01 ms/move) and a 4 ms first-move latency within modest resource budgets, and scaling to 256×256 arrays primarily along the BRAM axis. The principal unresolved issues are closing the hardware loop without PS mediation, sustaining full overlap under faster physical move execution, and validating the architecture in a live NAQC system under QEC workloads.