Automated logical Clifford gadgets for heterogeneous architectures via chain maps

Abstract: Transversal CNOTs are ubiquitous for entangling logical qubits of identical CSS codes pairwise. For distinct codes, the options are much more limited, and are typically known only for structurally related code families. We introduce an automated framework for synthesising inter-code logical CNOT circuits between arbitrary CSS codes using chain maps. Given a prescribed bipartite logical CNOT network between these codes, our method constructs the affine space of chain maps realising the desired logical action, and then searches this space for shallow and sparse physical circuit candidates. We benchmark this method on a range of heterogeneous CSS code pairs, recovering known transversal constructions, and finding new low-depth solutions, including distance-preserving and partially distance-preserving examples, which we demonstrate can be promoted to the full code distance using additional flag measurements. We discuss applications to code switching, magic-state injection, Pauli product measurements, and operations on concatenated codes, where bespoke chain maps offer favourable spacetime tradeoffs for logical interfaces tailored to heterogeneous architectures. Finally, we show how our framework straightforwardly extends to targeted logical CZ gates.

• The paper introduces an automated framework that synthesizes logical CNOT circuits between arbitrary CSS codes using chain map theory.
• It reduces gadget construction to linear algebra problems and combinatorial optimization, achieving shallow circuit depth and low resource count.
• Numerical benchmarks validate the approach with effective heterogeneous code interfacing and potential enhancements through flag-assisted fault-tolerance.

Automated Construction of Inter-Code Logical Clifford Gadgets via Chain Maps

Overview and Framework

The paper "Automated logical Clifford gadgets for heterogeneous architectures via chain maps" (2607.02482) introduces a general and automated methodology for synthesizing inter-code logical CNOT (and Clifford) circuits between arbitrary CSS codes by leveraging the algebraic structure of chain maps. This framework systematically extends logical gate compilation beyond self-similar codes and homogeneous code families, supporting the growing trend towards heterogeneous QECC architectures. The central objective is the explicit construction and optimization of depth- and resource-efficient physical circuits implementing desired logical Clifford operations between any pair of CSS codes, realized as affine subspaces of chain map solutions.

The approach is based on recognizing that physical transversal CNOTs constitute a special case of chain maps and that, for arbitrary CSS code pairs, chain map theory encodes all physically valid logical Clifford interfaces. A key technical accomplishment is reducing the synthesis of these gadgets to a sequence of linear algebraic problems: enumerating all admissible degree-1 chain maps, imposing affine constraints to achieve specific logical actions, and identifying efficient physical implementations via combinatorial optimization within these affine spaces.

Algebraic Formalism for Chain-Map Gadgets

CSS Codes as Chain Complexes

CSS codes are encoded as chain complexes over $\mathbb{F}_2$:

$$C_2 \xrightarrow{\partial_2} C_1 \xrightarrow{\partial_1} C_0$$

where the boundary maps encode stabilizer generators. Logical operators correspond to homology classes. Given two such codes $(A, B)$, a logical interface corresponds to a chain map—i.e., a triple $(\gamma_2, \gamma_1, \gamma_0)$—that preserves the commutative diagram structure of the complexes.

Characterizing Feasible Inter-Code CNOTs

The crucial object for physically implementing logical CNOTs is $\gamma_1: C_1^B \rightarrow C_1^A$. This map can be interpreted as an $n_A \times n_B$ binary matrix, where a nonzero entry denotes a physical CNOT from a qubit in $A$ to a qubit in $B$. The authors show that the set of all such $\gamma_1$ that admit an extension to a full chain map forms an explicit linear subspace—computed as the kernel of a binary matrix constructed from the codes' parity-check matrices. Importantly, only a subset of this space achieves a targeted logical action (e.g., a specific pattern of logical CNOTs), leading to affine subspaces parametrizing all chain-maps realizing the desired logical effect.

Logical Action and Constraint Imposition

Given bases of logical operators, the logical action induced by each $\gamma_1$ is computed via explicit formulas. The process of targeting a specific logical operation is then translated into affine constraints on $$C_2 \xrightarrow{\partial_2} C_1 \xrightarrow{\partial_1} C_0$$0, further restricting the admissible slice of chain maps.

Automated Synthesis and Optimization Procedure

Given parity-check matrices and a logical action target, the authors' framework performs the following steps:

1. Construct $$C_2 \xrightarrow{\partial_2} C_1 \xrightarrow{\partial_1} C_0$$1: Efficient computation of the linear subspace of all degree-1 chain maps between the codes.
2. Affine Restriction for Logical Targeting: Restrict the linear space to an affine family corresponding to chain maps that implement the desired logical operation.
3. Cost-Driven Combinatorial Optimization: Formulate and solve a CP-SAT optimization problem to select among the affine family a $$C_2 \xrightarrow{\partial_2} C_1 \xrightarrow{\partial_1} C_0$$2 of minimal circuit depth and/or minimal weight (number of CNOTs), optionally exploiting sparse basis heuristics for computational tractability.

The search within the affine family can be flexibly tailored to prioritize different architectural requirements, including minimizing fault-propagation (thus improving distance preservation), circuit parallelism (via depth minimization), and respect for hardware-specific support constraints.

Applications and Numerical Results

The framework is validated and benchmarked for a broad spectrum of use-cases in fault-tolerant quantum computation:

• Heterogeneous Code Switching and Magic State Injection: Direct construction of inter-code CNOTs between diverse code families enables efficient magic state injection protocols without the overhead of universal adapters, as illustrated by contrasting depth/circuit requirements for joint logical Pauli measurements versus direct CNOT chains (Figure 1).

  Figure 1: Methods to inject magic states. (Left) Logical circuit to inject $$C_2 \xrightarrow{\partial_2} C_1 \xrightarrow{\partial_1} C_0$$3 magic states using universal adapters; (Right) using an inter-block logical CNOT.

• Generalization to Arbitrary Code Pairs: Benchmarks demonstrate recovery of known transversal constructions, as well as new low-depth and distance-preserving CNOTs for arbitrary pairs—including between surface/toric codes, color codes, and high-rate qLDPC codes. Examples featuring both homogeneous and heterogeneous pairs are given, often revealing gadgets matching or improving on manual constructions in terms of depth and circuit-level code distance.
• Flag-Assisted Fault-Tolerance: When unflagged circuits are not fully distance-preserving, the affine solution space still typically includes partially fault-tolerant solutions, which can be promoted to full code distance using a modest number of flag qubits and additional stabilizer measurements. This approach maintains favorable spacetime resources, as evidenced in explicit flagged homomorphic CNOT constructions (see Figure 2).

  Figure 2: Schematic circuit describing a flagged homomorphic CNOT between code A and code B, leveraging additional flag measurements to restore code distance.

• Efficient Pauli Product Measurements and Clifford Gadgets: The chain map construction naturally extends to the design of gadgets for general Pauli product measurement, logical fan-out/in, and multi-qubit interfaces in concatenated or block-structured code settings. For grid-like hypergraph product codes, both standard (GPPM) and bespoke chain map solutions are explicitly compared (Figure 3).

  Figure 3: Comparison of GPPMs and bespoke chain maps for measuring Pauli products, showing that chain maps can provide equivalent or improved resource requirements.

• Circuit-Level Simulations and Thresholds: The logical error rates of synthesized gadgets are empirically benchmarked under realistic circuit-level noise models, showing that the performance of optimized inter-code CNOTs (with or without flagging) is consistently within a small factor of corresponding idling memory or transversal-CNOT baselines.

Implications and Directions for Future Work

The principal implication is that chain map synthesis provides a unifying, general, and practically tractable foundation for the automated construction of logical Clifford interfaces in both homogeneous and heterogeneous QEC architectures. The approach is agnostic to code structure, enabling algorithmic discovery and optimization of inter-code logical operations without domain-specific combinatorics or geometry assumptions.

Numerical results substantiate claims that, for code sizes relevant to near-term hardware proposals, the affine flexibility of the chain map space is frequently sufficient to yield shallow, low-weight, and often distance-preserving circuits even for nontrivial code pairs. The extension to partially distance-preserving circuits using efficient flagging further expands the practical reach.

From a theoretical perspective, the explicit algebraic characterization of Clifford gadgets as elements of hom-space affine families has implications for understanding composability, code capacity, and cross-family logical implementations. It also offers a fertile ground for developing QEC-aware optimization heuristics that can embed device-level constraints directly into the synthesis process.

Potential future directions include:

• Leveraging code automorphisms for scalable basis selection and solution space reduction to tackle larger instances
• Direct incorporation of QEC performance metrics (e.g., logical error rates, correlated error patterns) as optimization objectives
• Extending the formalism to non-CSS codes and general (possibly non-Clifford) logical circuits via chain or chain-cochain duality
• Deeper integration with hardware-level layout and qubit connectivity for fully device-aware gadget synthesis

Conclusion

This work systematizes the automated discovery of logical Clifford gadgets interfacing arbitrary CSS codes by fully exploiting the chain map structure. Through explicit linear-algebraic reduction and discrete optimization, the method both recovers and surpasses previous hand-optimized constructions in terms of circuit depth, resource count, and distance preservation, across a wide range of code families and target logical actions. The implications are significant for modular, heterogeneous fault-tolerant architectures, enabling the flexible interconnection of diverse code components with minimal manual effort and resource overhead.